Datasheet

CLKIO
DeviceReady
t
WAKE
3.2V,typical
CLKSEL
or
AVDD AVSS-
(1)
or
PWDN
CLKIO
DeviceReady
t
WAKE
3.2V,typical
or
AVDD AVSS-
(1)
PWDN,
CLKSEL
ADS1158
SBAS429D –JUNE 2008– REVISED MARCH 2011 www.ti.com
Table 6. Wake-Up Times
POWER-UP TIMING
t
WAKE
When powering up the device or taking the PWDN
INTERNAL t
WAKE
pin high to wake the device, a wake-up time is
CONDITION OSCILLATOR
(1)
EXTERNAL CLOCK
required before readings can be taken. When using
PWDN or CLKSEL t
OSC
2/f
CLK
the internal oscillator, the wake-up time is composed
AVDD – AVSS t
OSC
+ 2
18
/f
CLK
2
18
/f
CLK
of the oscillator start-up time and the PLL lock time,
and if the supplies are also being powered, there is a
(1) Wake-up times for the internal oscillator operation are typical
reset interval time of 2
18
f
CLK
cycles. Note that CLKIO
and may vary depending on crystal characteristics and layout
capacitance. The user should verify the oscillator start-up
is not valid during the wake-up period, as shown in
times (t
OSC
= oscillator start-up time).
Figure 37.
POWER-UP SEQUENCE
The analog and digital supplies should be applied
before any analog or digital input is driven. The power
supplies may be sequenced in any order. The internal
master reset signal is generated from the analog
power supply (AVDD – AVSS), when the level
reaches approximately 3.2V. The power-up master
reset signal is functionally the same as the Reset
Command and the RESET input pin.
Reset Input (RESET)
When RESET is held low for at least two f
CLK
cycles,
all registers are reset to their default values and the
(1) Shown with DVDD stable.
digital filter is cleared. When RESET is released high,
the device is ready to convert data.
Figure 37. Device Wake Time with
Internal Oscillator
Clock Select Input (CLKSEL)
This pin selects the source of the system clock: the
When using the device with an external clock, the
crystal oscillator or an external clock. Tie CLKSEL
wake-up time is 2/f
CLK
periods when waking up with
low to select the crystal oscillator. When using an
the PWDN pin and 2
18
/f
CLK
periods when powering
external clock (applied to the CLKIO pin), tie CLKSEL
the supplies, all after a valid CLKIO is applied, as
high.
shown in Figure 38.
Clock Input/Output (CLKIO)
This pin serves either as a clock output or clock input,
depending on the state of the CLKSEL pin. When
using an external clock, apply the clock to this pin
and set the CLKSEL pin high. When using the
internal oscillator, this pin has the option of providing
a clock output. The CLKENB bit of register CONFIG0
enables the clock output (default is enabled).
Start Input (START)
The START pin is an input that controls the ADC
(1) Shown with DVDD stable.
process. When the START pin is taken high, the
Figure 38. Device Wake Time with External Clock
converter starts converting the selected input
channels. When the START pin is taken low, the
conversion in progress runs to completion and the
Table 6 summarizes the wake-up times using the
converter is stopped. The device then enters one of
internal oscillator and the external clock operations.
the two idle modes (see the Idle Modes section for
more details). See the Conversion Control section for
details of using the START pin.
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