Datasheet

ADC
Multiplexer
(chopping)
AINn
AINn
MUXOUTP
MUXOUTN
ADCINP
Optional
Signal
Conditioning
ADCINN
GPIOPin
GPIOData(read)
GPIOData(write)
GPIOControl
ADS1158
www.ti.com SBAS429D –JUNE 2008– REVISED MARCH 2011
EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx)
The modulator of the ADS1158 incorporates a The ADS1158 has eight dedicated general-purpose
chopping front-end that removes offset errors to digital input/output (GPIO) pins. The digital I/O pins
provide excellent offset and offset drift performance. are individually configurable as either inputs or as
However, offset and offset drift that originate from outputs through the GPIOC (GPIO-Configure)
external signal conditioning are not removed by the register. The GPIOD (GPIO-Data) register controls
modulator. The ADS1158 has an additional chopping the level of the pins. When reading the GPIOD
feature that removes external offset errors (CHOP = register, the data returned are the level of the pins,
1). whether they are programmed as inputs or outputs.
As inputs, a write to the GPIOD has no effect. As
With external chopping enabled, the converter takes
outputs, a write to the GPIOD sets the output value.
two readings in succession on the same channel. The
first reading is taken with one polarity and the second During Standby and Power-Down modes, the GPIO
reading is taken with the opposite polarity. The remains active. If configured as inputs, these pins
converter averages the two readings and cancels the must be driven (do not float). If configured as outputs,
offset, as shown in Figure 35. With chopping enabled, the pins are driven. The GPIO pins are set as inputs
the effective reading reduces to half of the nominal after power-on or after a reset. Figure 36 shows the
reading rate. GPIO port structure.
Figure 35. External Chopping
Note that because the inputs are reversed under
Figure 36. GPIO Port Pin
control of the ADS1158, a delay time may be
necessary to provide time for external signal
conditioning to fully settle before the second phase of
POWER-DOWN INPUT (PWDN)
the reading sequence starts (see the Switch Time
The PWDN pin controls the power-down mode of the
Delay section).
converter. In power-down mode, all internal circuitry
External chopping can be used to reduce total offset
is deactivated including the oscillator and the clock
errors and offset drift over temperature. Note that
output. Hold PWDN low for at least two f
CLK
cycles to
chopping must be disabled (CHOP = 0) in order to
engage power-down. The register settings are
take the internal monitor readings.
retained during power-down. When the pin is returned
high, the converter requires a wake-up time before
readings can be taken, as shown in the Power-Up
Timing section. Note that in power-down mode, the
inputs of the ADS1158 must continue to be driven
and the device continues to drive the outputs.
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Product Folder Link(s): ADS1158