Datasheet

DRDY
1 2
StepInput
DataNotSettled SettledData
DRDY
1 2 6
StepInput
DataNotSettled SettledData
0
-20
-40
-60
-80
-100
-120
-140
Frequency(MHz)
Gain(dB)
4 80 12 16
DRATE[1:0]=11
125kSPS
Fixed-ChannelMode
ADS1158
SBAS429D –JUNE 2008– REVISED MARCH 2011 www.ti.com
ALIASING applying asynchronous step inputs, the settling time
is somewhat different. The step-input settling time
The digital filter low-pass characteristic repeats at
diagrams (Figure 32 and Figure 33) show the
multiples of the modulator rate of f
CLK
/2. Figure 31
converter step response with an asynchronous step
shows the response plotted out to 16MHz at the data
input. For most modes of operation, the analog input
rate of 125kSPS (Fixed-Channel mode). Notice how
must be stable for one complete conversion cycle to
the responses near dc, 8MHz, and 16MHz are the
provide settled data. In Fixed-Channel mode
same. The digital filter attenuates high-frequency
(DRATE[1:0] = 11), the input must be stable for five
noise on the ADS1158 inputs up to the frequency
complete conversion cycles.
where the response repeats. However, noise or
frequency components present on the analog input
where the response repeats alias into the passband.
For most applications, an anti-alias filter is
recommended to remove this noise. A simple
first-order input filter with a pole at 200kHz
provides –34dB rejection at the first image frequency.
Figure 32. Asynchronous Step-Input Settling
Time (DRATE[1:0] = 10, 01, 00)
Figure 33. Asynchronous Step-Input Settling
Time (Fixed-Channel Mode, DRATE[1:0] = 11)
Figure 31. Frequency Response Out to 16MHz
Table 4. Effective Data Rates with Switch-Time
Delay (Auto-Scan Mode)
(1)
Referring to Figure 29 and Figure 30, frequencies
TIME
present on the analog input above the Nyquist rate
DELAY TIME DRATE DRATE DRATE DRATE
DLY (128/f
CLK
DELAY [1:0] = [1:0] = [1:0] = [1:0] =
(sample rate/2) are first attenuated by the digital filter
[2:0] periods) (μS) 11 10 01 00
and then aliased into the passband.
000 0 0 23739 15123 6168 1831
001 1 8 19950 13491 5878 1805
SETTLING TIME
010 2 16 17204 12177 5614 1779
The design of the ADS1158 provides fully-settled
011 4 32 13491 10191 5151 1730
data when scanning through the input channels in
100 8 64 9423 7685 4422 1639
Auto-Scan mode. The DRDY flag asserts low when
101 16 128 5878 5151 3447 1483
the data for each channel are ready. It may be
110 32 256 3354 3104 2392 1247
necessary to use the automatic switch time delay
111 48 384 2347 2222 1831 1075
feature to provide time for settling of the external
buffer and associated components after channel
switching. When the converter is started (START pin
(1) Time delay and data rates scale with f
CLK
. If Chop = 1, the
transitions high or Start Command) with stable inputs,
data rates are half those shown. f
CLK
= 16MHz, Auto-Scan
the first converter output is fully settled. When mode.
18 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS1158