Datasheet

128(4 +4.26525+TD) 2´
11b DR CHOP-
f
CLK
128[4 +CHOP(4.26525+TD)] 2´
11b DR CHOP-
f
CLK
Analog
Modulator
sinc
5
Filter
Programmable
Averager
DataRate=f /128
CLK
ModulatorRate=f /2
CLK
Num_Ave
DataRate /(128 ´=f
CLK
Num_Ave)
(1)
ADS1158
SBAS429D –JUNE 2008– REVISED MARCH 2011 www.ti.com
Digital Filter
Make sure to use a clock source clean from jitter or
interference. Ringing or under/overshoot should be
The programmable low-pass digital filter receives the
avoided. A 50Ω resistor in series with the CLKIO pin
modulator output and produces a high-resolution
(placed close to the source) can often help.
digital output. By adjusting the amount of filtering,
tradeoffs can be made between resolution and data
ADC
rate—filter more for higher resolution, filter less for
higher data rate. The filter consists of two sections, a
The ADC block of the ADS1158 is composed of two
fixed filter followed by a programmable filter.
blocks: a modulator and a digital filter.
Figure 28 shows the block diagram of the filter. Data
are supplied to the filter from the analog modulator at
Modulator
a rate of f
CLK
/2. The fixed filter is a fifth-order sinc
The modulator converts the analog input voltage into
filter with a decimation value of 64 that outputs data
a pulse code modulated (PCM) data stream. When
at a rate of f
CLK
/128. The second stage of the filter is
the level of differential analog input (ADCINP –
a programmable averager (first-order sinc filter) with
ADCINN) is near the level of the reference voltage,
the number of averages set by the DRATE[1:0] bits.
the '1' density of the PCM data stream is at its
The data rate depends upon the system clock
highest. When the level of the differential analog input
frequency (f
CLK
) and the converter configuration. The
is near zero, the PCM '0' and '1' densities are nearly
data rate can be computed by Equation 1 or
equal. The fourth-order modulator shifts the
Equation 2:
quantization noise to a high frequency (out of the
passband) where the digital filter can easily remove it.
Data rate (Auto-Scan):
The modulator continuously chops the input, resulting
in excellent offset and offset drift performance. It is
(1)
important to note that offset or offset drift that
originates from the external circuitry is not removed
Data rate (Fixed-Channel mode):
by the modulator chopping. These errors can be
effectively removed by using the external chopping
feature of the ADS1158 (see the External Chopping
(2)
section).
Where:
DR = DRATE[1:0] register bits (binary).
CHOP = Chop register bit.
TD = time delay value given in Table 4 from the
DLY[2:0] register bits (128/f
CLK
periods).
(1) Data rate for Fixed-Channel mode, Chop = 0, Delay = 0.
Figure 28. Block Diagram of Digital Filter
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