Datasheet

50W
32.768kHz
(1)
4.7pF 4.7pF
22nF
CLKSEL XTAL1 XTAL2 PLLCAP
AVSS
CLKIO
ClockOutput
(15.729MHz)
0Vto 2.5V-
Oscillator
andPLL
MUX
CLKENB
Bit
InternalMasterClock(f )
CLK
CLKSEL
CLKIO
XTAL1 XTAL2 PLL
50W
CLKSEL XTAL1 XTAL2 PLLCAP
DVDD
CLKIO
ClockInput
(16MHz)
2.7V
to5V
NoConnection
ADS1158
www.ti.com SBAS429D –JUNE 2008– REVISED MARCH 2011
MASTER CLOCK (f
CLK
)
The ADS1158 oversamples the analog input at a high
rate. This oversampling requires a high-frequency
master clock to be supplied to the converter. As
shown in Figure 25, the clock comes from either an
internal oscillator (with external crystal), or an
external clock source.
(1) Parallel resonant type. C
L
= 12.5pF, ESR = 35kΩ (max). Place
the crystal and load capacitors as close as possible to the device
pins.
Figure 26. Crystal Oscillator Connection
Table 1. System Clock Source
CLKSEL CLKENB
PIN CLOCK SOURCE BIT CLKIO FUNCTION
32.768kHz Disabled
0 0
crystal oscillator (internally grounded)
32.768kHz
0 1 Output (15.729MHz)
Figure 25. Clock Generation Block Diagram
crystal oscillator
1 External clock input X Input (16MHz)
The CLKSEL pin determines the source of the
system clock, as shown in Table 1. The CLKIO pin
Table 2. Approved Crystal Vendors
functions as an input or as an output. When the
VENDOR CRYSTAL PRODUCT
CLKSEL pin is set to '1', CLKIO is configured as an
Epson C-001R
input to receive the master clock. When the CLKSEL
Epson MC-306 32.7680K-A0
pin is set to '0', the crystal oscillator generates the
clock. The CLKIO pin can then be configured to
Epson FC-135 32.7680KA-A0
output the master clock. When the clock output is not
ECS ECS-.327-12.5-17-TR
needed, it can be disabled to reduce device power
consumption.
External Clock Input
Crystal Oscillator
When using an external clock to operate the device,
apply the master clock to the CLKIO pin. For this
An on-chip oscillator and phase-locked loop (PLL)
mode, the CLKSEL pin is tied high. CLKIO then
together with an external crystal can be used to
becomes an input, as shown in Figure 27.
generate the system clock. For this mode, tie the
CLKSEL pin low. A 22nF PLL filter capacitor,
connected from the PLLCAP pin to the AVSS pin, is
required. The internal clock of the PLL can be output
to the CLKIO to drive other converters or controllers.
If not used, disable the clock output to reduce device
power consumption; see Table 1 for settings. The
clock output is enabled by a register bit setting
(default is ON). Figure 26 shows the oscillator
connections. Place these components as close to the
pins as possible to avoid interference and coupling.
Do not connect XTAL1 or XTAL2 to any other logic.
Figure 27. External Clock Connection
The oscillator start-up time may vary, depending on
the crystal and ambient temperature. The user should
verify the oscillator start-up time.
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