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ADS1158

16-Bit

ADC

Digital

Filter

Internal

Monitoring

16:1

Analog

Input

MUX

AINCOM

ADC

ExtCLK

In/Out

AVSS DGND

32.768kHz

AVDD DVDD

MUX

OUT

SPI

Interface

DRDY

SCLK

DIN

DOUT

ControlOscillator

GPIO

START

RESET

PWDN

GPIO[7:0]V

REF

ADS1158

AnalogInputs

ADS1158

www.ti.com

SBAS429D –JUNE 2008– REVISED MARCH 2011

16-Channel, 16-Bit Analog-to-Digital Converter

Check for Samples: ADS1158

FEATURES

DESCRIPTION

The ADS1158 is a 16-channel (multiplexed),

• 16 Bits, No Missing Codes

low-noise, 16-bit, delta-sigma (ΔΣ) analog-to-digital

• Fixed-Channel or Automatic Channel Scan

converter (ADC) that provides single-cycle settled

• Fixed-Channel Data Rate: 125kSPS

data at channel scan rates from 1.8k to 23.7k

samples per second (SPS) per channel. A flexible

• Auto-Scan Data Rate: 23.7kSPS/Channel

input multiplexer accepts combinations of eight

• Single-Conversion Settled Data

differential or 16 single-ended inputs with a full-scale

• 16 Single-Ended or 8 Differential Inputs

differential range of 5V or true bipolar range of ±2.5V

when operating with a 5V reference. The fourth-order

• Unipolar (+5V) or Bipolar (±2.5V) Operation

delta-sigma modulator is followed by a fifth-order sinc

• 0.3LSB (INL)

digital filter optimized for low-noise performance.

• DC Stability:

The differential output of the multiplexer is accessible

1μV/°C Offset Drift, 2ppm/°C Gain Drift

to allow signal conditioning before the input of the

• Open-Sensor Detection

ADC. Internal system monitor registers provide

• Conversion Control Pin

supply voltage, temperature, reference voltage, gain,

and offset data.

• Multiplexer Output for External Signal

Conditioning

An onboard PLL generates the system clock from a

32.768kHz crystal, or can be overridden by an

• On-Chip Temperature, Reference, Offset, Gain,

external clock source. A buffered system clock output

and Supply Voltage Readback

(15.7MHz) is provided to drive a microcontroller or

• 42mW Power Dissipation

additional converters.

• Standby, Sleep, and Power-Down Modes

Serial digital communication is handled via an

• Eight General-Purpose Inputs/Outputs (GPIO)

SPI™-compatible interface. A simple command word

• 32.768kHz Crystal Oscillator or External Clock

structure controls channel configuration, data rates,

digital I/O, monitor functions, etc.

APPLICATIONS

Programmable sensor bias current sources can be

• Medical, Avionics, and Process Control

used to bias sensors or verify sensor integrity.

• Machine and System Monitoring

The ADS1158 operates from a unipolar +5V or

• Fast Scan Multi-Channel Instrumentation

bipolar ±2.5V analog supply and a digital supply

compatible with interfaces ranging from 2.7V to

• Industrial Systems

5.25V. The ADS1158 is available in a QFN-48

• Test and Measurement Systems

package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (51 pages)

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ADS1158 AD S1 158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com 16-Channel, 16-Bit Analog-to-Digital Converter Check for Samples: ADS1158 FEATURES DESCRIPTION • • • • • • • • • The ADS1158 is a 16-channel (multiplexed), low-noise, 16-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) that provides single-cycle settled data at channel scan rates from 1.8k to 23.7k samples per second (SPS) per channel.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +105°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = +4.096V, and VREFN = –2.5V, unless otherwise noted.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +105°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = +4.096V, and VREFN = –2.5V, unless otherwise noted. ADS1158 PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic levels VIH 0.7DVDD DVDD V VIL DGND 0.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com PIN ASSIGNMENTS (continued) 6 PIN # NAME ANALOG/DIGITAL INPUT/OUTPUT 21 GPIO7 Digital I/O 22 SCLK Digital input SPI interface clock input: data clocked in on rising edge, clocked out on falling edge. 23 DIN Digital input SPI interface data input: data are input to the device. 24 DOUT Digital output SPI interface data output: data are output from the device. 25 DRDY Digital output Data ready output: active low.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION CS(1) tCSPW tCSSC tSCLK tSPW SCLK tSPW tDIST DIN tDIHD Hi-Z tDOPD Hi-Z DOUT tCSDO tDOHD (1) CS can be tied low. Figure 1. Serial Interface Timing SERIAL INTERFACE TIMING CHARACTERISTICS At TA= –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. OFFSET WITH 0.5V REFERENCE, CHOPPING ON OFFSET WITH 4.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. INTEGRAL NONLINEARITY vs VREF INTEGRAL NONLINEARITY vs INPUT LEVEL 10 8 9 6 4 Linearity Error (ppm) Linearity Error (ppm) 8 7 6 5 4 3 VREF = 4.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. SENSOR BIAS CURRENT SOURCE RATIO vs TEMPERATURE SENSOR BIAS CURRENT SOURCE RATIO HISTOGRAM 14 17.5 17.0 10 Ratio (mA/mA) Number of Occurrences 12 18.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com OVERVIEW The ADS1158 is a flexible, 16-bit, low-noise ADC optimized for fast multi-channel, high-resolution measurement systems. The converter provides a maximum channel scan rate of 23.7kSPS, giving a complete 16-channel scan in less than 700μs. The ADS1158 converter consists of a fourth-order, delta-sigma modulator followed by a programmable digital filter.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com MULTIPLEXER INPUTS A simplified diagram of the input multiplexer is illustrated in Figure 22. The multiplexer connects one of 16 single-ended external inputs, one of eight differential external inputs, or one of the on-chip internal variables to the ADC inputs. The output of the channel multiplexer can be routed to external pins and then to the input of the ADC. This flexibility allows for use of external signal conditioning.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com VREFP VREFN Multiplexer Reference/Gain Monitor AIN0 AIN1 AIN2 Temperature Sensor Monitor AVDD AIN3 1x AIN4 2x AIN5 8x 1x AIN6 AVSS AIN7 Supply Monitor AIN8 AVDD AVSS AIN9 AIN10 AIN11 NOTE: ESD diodes not shown. Internal Reference AIN12 AVSS AIN13 AIN14 ADC AIN15 AINCOM ADCINN ADCINP Offset Monitor MUXOUTP Sensor Bias (AVDD - AVSS)/2 MUXOUTN AVSS AVDD Figure 22.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com ADC INPUTS The ADS1158 ADC inputs (ADCINP, ADCINN) measure the input signal using internal capacitors that are continuously charged and discharged. The left side of Figure 24 shows a simplified schematic of the ADC input circuitry; the right side of Figure 24 shows the input circuitry with the capacitors and switches replaced by an equivalent circuit. Figure 23 shows the ON/OFF timings of the switches shown in Figure 24.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com MASTER CLOCK (fCLK) The ADS1158 oversamples the analog input at a high rate. This oversampling requires a high-frequency master clock to be supplied to the converter. As shown in Figure 25, the clock comes from either an internal oscillator (with external crystal), or an external clock source. 50W CLKSEL XTAL1 XTAL2 32.768kHz CLKIO Clock Output (15.729MHz) AVSS 0V to -2.5V PLLCAP (1) 22nF CLKENB Bit 4.7pF (1) Parallel resonant type.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Make sure to use a clock source clean from jitter or interference. Ringing or under/overshoot should be avoided. A 50Ω resistor in series with the CLKIO pin (placed close to the source) can often help. ADC The ADC block of the ADS1158 is composed of two blocks: a modulator and a digital filter. Modulator The modulator converts the analog input voltage into a pulse code modulated (PCM) data stream.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Table 3 shows a listing of the averaging and data rates for each of the four DRATE[1:0] register settings for the Auto-Scan and Fixed-Channel modes, with CHOP, DLY = 0. Note that the data rate scales directly with fCLK. For example, reducing fCLK by 2x reduces the maximum data rate by 2x. Figure 30 shows the response with averaging set to 4 (DRATE[1:0] = 10).
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com ALIASING The digital filter low-pass characteristic repeats at multiples of the modulator rate of fCLK/2. Figure 31 shows the response plotted out to 16MHz at the data rate of 125kSPS (Fixed-Channel mode). Notice how the responses near dc, 8MHz, and 16MHz are the same. The digital filter attenuates high-frequency noise on the ADS1158 inputs up to the frequency where the response repeats.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com EXTERNAL MULTIPLEXER LOOP The external multiplexer loop consists of two differential multiplexer output pins and two differential ADC input pins. The user may use external components (buffering/filtering, single-ended to differential conversion, etc.) to form a signal conditioning loop. For best performance, the ADC input should be buffered and driven differentially.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com SENSOR BIAS An integrated current source provides a means to bias an external sensor (for example, a diode junction); or, it verifies the integrity of a sensor or sensor connection. When the sensor fails to an open condition, the current sources drive the inputs of the converter to positive full-scale. The biasing is in the form of differential currents (programmable 1.5μA or 24μA), connected to the output of the multiplexer.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx) The modulator of the ADS1158 incorporates a chopping front-end that removes offset errors to provide excellent offset and offset drift performance. However, offset and offset drift that originate from external signal conditioning are not removed by the modulator. The ADS1158 has an additional chopping feature that removes external offset errors (CHOP = 1).
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Table 6. Wake-Up Times POWER-UP TIMING When powering up the device or taking the PWDN pin high to wake the device, a wake-up time is required before readings can be taken. When using the internal oscillator, the wake-up time is composed of the oscillator start-up time and the PLL lock time, and if the supplies are also being powered, there is a reset interval time of 218 fCLK cycles.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Data Ready Output (DRDY) The DRDY pin is an output that asserts low to indicate when new channel data are available to read (the previous conversion data are lost). DRDY returns high after the first falling edge of SCLK during a data read operation. If the data are not read (no SCLK pulses), DRDY remains low until new channel data are available once again. DRDY then pulses high, then low to indicate new data are available; see Figure 39.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Reference Reading (REF) INTERNAL SYSTEM READINGS Analog Power-Supply Reading (VCC) The analog power-supply voltage of the ADS1158 can be monitored by reading the VCC register. The supply voltage is routed internal to the ADS1158 and is measured and scaled using an internal reference. The supply readback channel outputs the difference between AVDD and AVSS (AVDD – AVSS), for both single and dual configurations.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Offset Reading (OFFSET) Data Ready, Index to Next Channel The differential output of the multiplexer is shorted together and set to a common-mode voltage of (AVDD – AVSS)/2. Ideally, the code from this register function is 0h, but varies because of the noise of the ADC and offsets stemming from the ADC and external signal conditioning. This register can be used to calibrate or track the offset of the ADS1158 and external signal conditioning.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com GPIO Linked START Pin Control The START pin can be controlled directly by software by connecting externally a GPIO port pin to the START pin. (Note that an external pull-down resistor is recommended to keep the GPIO from floating until the GPIO is configured as an output).
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Auto-Scan Mode Fixed-Channel Mode The ADS1158 provides 16 analog inputs that can be configured in combinations of eight differential inputs or 16 single-ended inputs. The device also provides an additional five internal system measurements. Taken together, the device allows a total of 29 possible channel measurements.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Serial Clock (SCLK) Operation Reading DATA The serial clock (SCLK) is an input that is used to clock data into (DIN) and out of (DOUT) the ADS1158. This input is a Schmitt-trigger input that has a high degree of noise immunity. However, it is recommended to keep SCLK as clean as possible to prevent glitches from inadvertently shifting the data.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Channel Data Read Command Concurrent with the first SCLK transition, channel data are output on the DOUT output pin. A total of 16 or 24 SCLK transitions complete the data read operation. The number of shifts depend on whether the status byte is enabled. The data must be completely shifted out before the next occurrence of DRDY or the remaining data are corrupted.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Register Read Command Beginning with the eighth SCLK rising edge (command byte completed), the MSB of the data are shifted in. The remaining seven SCLK rising edges complete the write to a single register. If MUL = '1', the data to the next register can be written by supplying additional SCLKs. The operation terminates when the last register is accessed (address = 09h), as shown in Figure 46.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com CHANNEL DATA The data read operation outputs either three bytes (one byte for status and two bytes for data), or two bytes for data only. The selection of the 3-byte or 2-byte data read is set by the bit STAT in register CONFIG0 (see Table 12, Status Byte, for options). In the 3-byte read, the first byte is the status byte and the following two bytes are the data bytes. The MSB (Data15) of the data are shifted out first. Table 9.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com BITS DATA[15:0] OF DATA BYTES The ADC output data are 16 bits wide (DATA[15:0]). DATA15 is the most significant bit (MSB) and DATA0 is the least significant bit (LSB). The data are coded in binary twos complement (BTC) format. Table 10.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com COMMAND AND REGISTER DEFINITIONS Commands are used to read channel data, access the configuration registers, and control the conversion process. If the command is a register read or write operation, one or more data bytes follow the command byte. If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation (see the MUL bit).
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com REGISTERS Table 11.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com Bit 3 CLKENB This bit enables the clock output on pin CLKIO. The clock output originates from the device crystal oscillator and PLL circuit. 0 = Clock output on CLKIO disabled. 1 = Clock output on CLKIO enabled (default). Note: If the CLKSEL pin is set to '1', the CLKIO pin is a clock input only. In this case, setting this bit has no effect. Bit 2 CHOP This bit enables the chopping feature on the external multiplexer loop.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com CONFIG1: CONFIGURATION REGISTER 1 (Address = 01h) 7 6 5 4 3 2 1 0 IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 Default = 83h. Bit 7 IDLMOD This bit selects the Idle mode when the device is not converting, Standby or Sleep. The Sleep mode offers lower power consumption but has a longer wake-up time to re-enter the run mode; see the Idle Modes section.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com MUXSCH: MULTIPLEXER FIXED-CHANNEL REGISTER (Address = 02h) 7 6 5 4 3 2 1 0 AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 Default = 00h. This register selects the input channels of the multiplexer to be used for the Fixed-Channel mode. The MUXMOD bit in register CONFIG0 must be set to '1'.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com GPIOC: GPIO CONFIGURATION REGISTER (Address = 07h) 7 6 5 4 3 2 1 0 CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 Default = FFh. This register configures the GPIO pins as inputs or as outputs. Note that the default configurations of the port pins are inputs and as such they should not be left floating. See the GPIO Digital Port section. 0 = GPIO is an output; 1 = GPIO is an input (default).
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION HARDWARE CONSIDERATIONS The following summarizes the design and layout considerations when using the ADS1158: a. Power Supplies: The converter accepts a single +5V supply (AVDD = +5V and AVSS = AGND) or dual, bipolar supplies (typically AVDD = +2.5V, AVSS = –2.5V). Dual supply operation accommodates true bipolar input signals, within a ±2.5V range.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com f. Clock Source: The ADS1158 requires a clock signal for operation. The clock can originate from either the crystal oscillator or from an external clock source. The internal oscillator uses a PLL circuit and an external 32.768kHz crystal to generate a 15.7MHz master clock. The PLL requires a 22nF capacitor from the PLLCAP pin to AVSS.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com DIGITAL INTERFACE CONNECTIONS The ADS1158 SPI-compatible interface easily connects to a wide variety of microcontrollers and DSPs. Figure 50 shows the basic connection to TI's MSP430 family of low-power microcontrollers. Figure 51 shows the connection to microcontrollers with an SPI interface such as the 68HC11 family, or TI's MSC12xx family.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com ANALOG INPUT CONNECTIONS Figure 54 shows the ADS1158 interfacing to high-level ±10V inputs, commonly used in industrial environments. In this case, bipolar power supplies are used to avoid the need for input signal level-shifting that is otherwise required with a single supply.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com +5V RFI + 0.1mF 10mF 2kW RFI AVSS AIN0 AVDD 2kW RFI REFP AIN1 RFI 10mF ¼ ¼ REFN ADCINN AINCOM ADCINP AIN15 MUXOUTP AIN14 2kW RFI 0.1mF ADS1158 MUXOUTN ¼ 2kW + RFI +5V 2.2nF 47W OPA365 R2 10kW R1 2.2kW R2 10kW 47W OPA365 NOTE: G = 1 + 2R2/R1. 0.1μF supply bypass capacitor not shown. Figure 55.
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ADS1158 SBAS429D – JUNE 2008 – REVISED MARCH 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (November, 2010) to Revision D Page • Changed default value for ID Register in Table 11 ............................................................................................................ 34 • Revised description of Device ID Register ................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1158IRTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS1158IRTCT VQFN RTC 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1158IRTCR VQFN RTC 48 2500 336.6 336.6 28.6 ADS1158IRTCT VQFN RTC 48 250 336.6 336.6 28.
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