Datasheet

Voltage Reference

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5 Voltage Reference

The ADS1258EVM has a DAC-controlled voltage reference circuit. The DAC used is a TI DAC8571,

controlled through the I

C. The address is set to 1001100. The output of the DAC is multiplied by two,

giving a range of approximately 0V to 5V. The DAC circuit is designed for low drift, but is uncalibrated. For

absolute accuracy, measure the DAC output and adjust as needed. The DAC high resolution reduces the

need for mechanical trimming.

Because of the high capacitance load on the buffer amplifier, the DAC step must be limited. The code

must not be changed by more than one at a time. (The PDK firmware incorporates a stepper task that

limits the slew-rate of the DAC by software.) If the DAC step is too high, the circuit saturates at a certain

voltage. To reset the circuit, return the DAC output to 0V.

Switches S1 and S2 allow various combinations of the DAC, external supply pins, and the power supply to

be selected, as shown in Table 7.

Table 7. Reference Selection

POSITION S1 REFP S2 REFN

Left AVDD AVSS

Center DAC GND

Right EXTREFP (J1.20) EXTREFN (J1.18)

6 Clock Source

The ADS1258 can use either an internal PLL-based clock source or an externally supplied clock. The

ADS1258EVM supports either type of clock.

For PLL operation, the ADS1258EVM is supplied with a 32.768kHz crystal. This clock mode is selected by

pulling GPIO2 on J6 (pin 8) low. In this mode, the generated clock can be measured on TP1, if the proper

bit is set in the ADS1258. The clock does not interfere with TOUT.

For external operation, a clock signal must be supplied on TOUT on J6 (pin 17), and GPIO2 must be

driven high. The level-shifted clock can be measured at TP1.

ADS1158EVM, ADS1258EVM, ADS1158EVM-PDK, and ADS1258EVM-PDK SBAU126C– May 2007– Revised May 2011

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