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J6 7-

J6 1-

Digital Interface

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Many pins on J6 have weak pull-up resistors. These resistors provide default settings for many of the

control pins. Many pins on J6 correspond directly to ADS1258 pins, as shown in Table 4. See the

ADS1258 data sheet for complete details on these pins.

Table 4. J6—Serial Interface Pins

PIN NUMBER PIN NAME SIGNAL NAME I/O TYPE PULL-UP FUNCTION

Optional ADS1258 START pin

J6.1 CNTL CNTL In None

control; see text

J6.2 GPIO0 PDWN In High ADS1258 power-down pin

J6.3 CLKX SCLK In None ADS1258 SPI clock

J6.4 DGND DGND In/Out None Digital ground

J6.5 CLKR — — None Unused

J6.6 GPIO1 RST In High ADS1258 reset pin

Optional ADS1258 chip-select

J6.7 FSX CS In Low

control; see text

Clock select:

J6.8 GPIO2 CLKSEL In High

0 = internal / out, 1 = external

J6.9 FSR — — None Unused

J6.10 DGND DGND In/Out None Digital ground

J6.11 DX DIN In None ADS1258 SPI data in

Power-supply mode:

J6.12 GPIO3 N/A In High

0 = bipolar, 1 = unipolar

J6.13 DR DOUT Out None ADS1258 SPI data out

J6.14 GPIO4 — — None Unused

J6.15 INT DRDY Out None ADS1258 data-ready output

J6.16 SCL SCL I

C N/A I

C clock

J6.17 TOUT CLK In None External clock input

J6.18 DGND DGND In/Out None Digital ground

J6.19 GPIO5 — — None Unused

J6.20 SDA SDA I

C N/A I

C data

3.2 GPIO

The GPIO connector, J3, carries the GPIO pins for the ADS1258. J3 is arranged so that GPIO0 and

GPIO1 can be used to control START and CS, respectively; see Figure 2 and Figure 5. The PDK firmware

controls START through GPIO0. CNTL(J6-1) and FSX(J6-7) are also brought to J3, so they can also be

used to control START and CS. Both FSX and CNTL are pulled down, so these pins can be used to keep

START and CS low if they are not to be used.

Figure 2. J3 Pin Configuration

ADS1158EVM, ADS1258EVM, ADS1158EVM-PDK, and ADS1258EVM-PDK SBAU126C– May 2007– Revised May 2011

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