Datasheet

DVDD
START
RESET
CS
DRDY
SCLK
3 00 00 00
Conversionresult
forchannel1
Power-upsequence ADCinitialsetup Multiplexerchangeischannel2 DataRetrievalfor
Channel2Conversion
Initialsetting:
AIN0isthepositivechannel,
AIN1isthenegativechannel,
internalreferenceselected,
PGAgain=32,
datarate=2kSPS,
VBIASisconnectedtothe
negativepinsAIN1andAIN3.
AIN2isthepositivechannel,
AIN3isthenegativechannel.
Conversionresult
forchannel2
01 02 03
WREG WREG
DIN
DOUT
t
DRDY
0.513ms
for
MUX0
Write
NOP
16ms
(1)
ADS1146
ADS1147
ADS1148
SBAS453F –JULY 2009–REVISED APRIL 2012 www.ti.com
APPLICATION INFORMATION
SPI COMMUNICATION EXAMPLES negative terminal of both sensors (that is, channels
AIN1 and AIN3). All these settings can be changed
This section contains several examples of SPI
by performing a block write operation on the first four
communication with the ADS1146/7/8, including the
registers of the device. After the DRDY pin goes low,
power-up sequence.
the conversion result can be immediately retrieved by
sending in 16 SPI clock pulses because the device
Channel Multiplexing Example
defaults to RDATAC mode. As the conversion result
is being retrieved, the active input channels can be
This first example applies only to the ADS1147 and
switched to AIN2 and AIN3 by writing into the MUX0
ADS1148. It explains a method to use the device with
register in a full-duplex manner, as shown in
two sensors connected to two different analog
Figure 51. The write operation is completed with an
channels. Figure 51 shows the sequence of SPI
additional eight SPI clock pulses. The time from the
operations performed on the device. After power-up,
write operation into the MUX0 register to the next
2
16
system clocks are required before communication
DRDY low transition is shown in Figure 51 and is
may be started. During the first 2
16
system clock
0.513ms in this case. After DRDY goes low, the
cycles, the devices are internally held in a reset state.
conversion result can be retrieved and the active
In this example, one of the sensors is connected to
channel can be switched as before.
channels AIN0 and AIN1 and the other sensor is
connected to channels AIN2 and AIN3. The ADC is
operated at a data rate of 2kSPS. The PGA gain is
set to 32 for both sensors. VBIAS is connected to the
(1) For f
OSC
= 4.096MHz.
Figure 51. SPI Communication Sequence for Channel Multiplexing
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