Datasheet

SCLK
DIN
1
1
D[15] D[14]D[15]D[14] D[13]
NOP NOP NOP
D[2] D[1] D[0] D[0]
2
2
3 14 15 16 1 2 8
16
DOUT/
(1)
DRDY
DRDY
SCLK
DOUT/
(1)
DRDY
DIN NOP
1
reg[7] reg[1] reg[0]
2 1 2 7 87 8
NOP
ADS1146
ADS1147
ADS1148
SBAS453F –JULY 2009–REVISED APRIL 2012 www.ti.com
(1) DRDY MODE bit enabled, CS tied low.
Figure 39. DOUT/DRDY Forced High After Retrieving the Conversion Result
(1) DRDY MODE bit enabled, CS tied low.
Figure 40. DOUT/DRDY Forced High After Reading Register Data
SPI Reset SPI Communication During Sleep Mode
SPI communication can be reset in several ways. In When the START pin is low or the device is in sleep
order to reset the SPI interface (without resetting the mode, only the RDATA, RDATAC, SDATAC,
registers or the digital filter), the CS pin can be pulled WAKEUP, and NOP commands can be issued. The
high. Taking the RESET pin low causes the SPI RDATA command can be used to repeatedly read the
interface to be reset along with all the other digital last conversion result during sleep mode. Other
functions. In this case, the registers and the commands do not function because the internal clock
conversion are reset. is shut down to save power during sleep mode.
32 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS1146 ADS1147 ADS1148