Datasheet

SCLK
D[15]
1 2 14 1 2 815 163
D[14] D[13] D[2] D[1] D[0]
DOUT/
(1)
DRDY
DRDY
SCLK
DIN
1
1
D[15] D[14]D[15]D[14] D[13]
NOP NOP
D[2] D[1] D[0] D[0]
2
2
3 14 15
16
16
DOUT/
(1)
DRDY
DRDY
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www.ti.com SBAS453F –JULY 2009–REVISED APRIL 2012
DOUT/DRDY by providing 16 SCLKs. In order to force
This pin has two modes: data out (DOUT) only, or DOUT/DRDY high (so that DOUT/DRDY can be
data out (DOUT) combined with data ready (DRDY). polled for a '0' instead of waiting for a falling edge), a
The DRDY MODE bit determines the function of this no operation command (NOP) or any other command
pin. In either mode, the DOUT/DRDY pin goes to a that does not load the data output register can be
high-impedance state when CS is taken high. sent after reading out the data. Because SCLKs can
only be sent in multiples of eight, a NOP can be sent
When the DRDY MODE bit is set to '0', this pin
to force DOUT/DRDY high if no other command is
functions as DOUT only. Data are clocked out at
pending. The DOUT/DRDY pin goes high after the
rising edge of SCLK, MSB first, as shown in
first rising edge of SCLK after reading the conversion
Figure 37.
result completely (see Figure 39). The same condition
also applies after an RREG command. After all the
When the DRDY MODE bit is set to '1', this pin
register bits have been read out, the rising edge of
functions as both DOUT and DRDY. Data are shifted
SCLK forces DOUT/DRDY high. Figure 40 illustrates
out from this pin, MSB first, at the rising edge of
an example where sending four NOP commands after
SCLK. This combined pin allows for the same control
an RREG command forces the DOUT/DRDY pin
but with fewer pins.
high.
When the DRDY MODE bit is enabled and a new
The DRDY MODE bit modifies only the DOUT/DRDY
conversion is complete, DOUT/DRDY goes low if it is
pin functionality. The DRDY pin functionality remains
high. If it is already low, then DOUT/DRDY goes high
unaffected.
and then goes low, as shown in Figure 38. Similar to
the DRDY pin, a falling edge on the DOUT/DRDY pin
signals that a new conversion result is ready. After
DOUT/DRDY goes low, the data can be clocked out
(1) CS tied low.
Figure 37. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)
(1) CS tied low.
Figure 38. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)
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