Datasheet

ADC
S
OFC
Register
Final
Output
OutputData
Clippedto16Bits
´
+
-
FSCRegister
400000h
FinalOutputData= (Input OFC[2:1])- ´
FSC[2:0]
400000h
- 1.251V > |Offset Scaling|
2V
Gain Scaling
ADS1146
ADS1147
ADS1148
www.ti.com SBAS453F –JULY 2009–REVISED APRIL 2012
CALIBRATION LSB correction and are used by the ADS1146/7/8
calibration commands. If an ADS1146/7/8 calibration
The conversion data are scaled by offset and gain
command is issued and the offset register is then
registers before yielding the final output code. As
read for storage and re-use later, it is recommended
shown in Figure 34, the output of the digital filter is
that all 24 bits of the OFC be used. When the
first subtracted by the offset register (OFC) and then
calibration commands are not used and the offset is
multiplied by the full-scale register (FSC). A digital
corrected by writing a user-calculated value to the
clipping circuit ensures that the output code does not
OFC register, it is recommended that only that only
exceed 16 bits. Equation 7 shows the scaling.
OFC[2:1] be used and that OFC[0] be left as all
zeros.
Note that while the offset calibration register value
can correct offsets ranging from –FS to +FS (as
shown in Table 8), make sure to avoid overloading
the analog inputs.
Table 8. Final Output Code versus Offset
Calibration Register Setting
Figure 34. Calibration Block Diagram
FINAL OUTPUT CODE WITH
OFFSET REGISTER V
IN
= 0
7FFFFFh 8000000h
(7)
000001h FFFFFFh
000000h 000000h
The values of the offset and full-scale registers are
set by writing to them directly, or they are set
FFFFFFh 000000h
automatically by calibration commands.
8000000h 7FFFFFh
The gain and offset calibration features are intended
1. Excludes effects of noise and inherent offset
for correction of minor system level offset and gain
errors.
errors. When entering manual values into the
calibration registers, care must be taken to avoid
Full-Scale Calibration Register: FSC[2:0]
scaling down the gain register to values far below a
The full-scale or gain calibration is a 24-bit word
scaling facter of 1.0. Under extreme situations it
composed of three 8-bit registers. The full-scale
becomes possible to over-range the ADC. To avoid
calibration value is 24-bit, straight binary, normalized
this, make sure to avoid encountering situations
to 1.0 at code 400000h. Table 9 summarizes the
where the analog inputs are connected to voltages
scaling of the full-scale register. Note that while the
greater than the reference/PGA.
full-scale calibration register can correct gain errors
Care must also be taken when increasing the digital
> 1 (with gain scaling < 1), make sure to avoid
gain. When implementing custom digital gains less
overloading the analog inputs.
than 20% higher than nominal and offsets less than
40% of full scale, no special care is required. When
Table 9. Gain Correction Factor versus Full-Scale
operating at digital gains greater than 20% higher
Calibration Register Setting
than nominal and offsets greater than 40% of full
FULL-SCALE REGISTER GAIN SCALING
scale, make sure that the offset and gain registers
800000h 2.0
follow the conditions of equation 8.
400000h 1.0
200000h 0.5
(8)
000000h 0
Offset Calibration Register: OFC[2:0]
The offset calibration is a 24-bit word, composed of
three 8-bit registers. The upper 16 bits, OFC[2:1], are
the most important for calibration and can correct
offsets ranging from –FS to +FS, as shown in
Table 8. The lower eight bits, OFC[0], provide sub-
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