Datasheet

ADS1146
ADS1147
ADS1148
SBAS453F –JULY 2009–REVISED APRIL 2012 www.ti.com
Data Format
The ADS1146/7/8 implement a timout function for all
listed commands in the event that data is corrupted
The ADS1146/7/8 output 16 bits of data in binary
and chip select is permanently tied low. However, it is
twos complement format. The least significant bit
important in systems where chip select is tied low
(LSB) has a weight of (V
REF
/PGA)/(2
15
– 1). The
permanently that register writes always be fully
positive full-scale input produces an output code of
completed in 8 bit increments. The SCLK line should
7FFFh and the negative full-scale input produces an
also be kept clean and situations should be avoided
output code of 8000h. The output clips at these codes
where noise on the SCLK line could cause the device
for signals exceeding full-scale. Table 13 summarizes
to interpret the transient as a false SCLK pulse. In
the ideal output codes for different input signals.
systems where such events are likely to occur, it is
recommended that chip select be used to frame
Table 13. Ideal Output Code vs Input Signal
communications to the device.
INPUT SIGNAL, V
IN
SCLK
(AIN
P
– AIN
N
) IDEAL OUTPUT CODE
This signal is the serial clock signal. SCLK provides
≥ +V
REF
/PGA 7FFFh
the clock for serial communication. It is a Schmitt-
(+V
REF
/PGA)/(2
15
– 1) 0001h
trigger input, but it is highly recommended that SCLK
0 0000h
be kept as clean as possible to prevent glitches from
(–V
REF
/PGA)/(2
15
– 1) FFFFh
inadvertently shifting the data. Data are shifted into
DIN on the falling edge of SCLK and shifted out of
≤ –(V
REF
/PGA) × (2
15
/2
15
– 1) 8000h
DOUT on the rising edge of SCLK.
1. Excludes effects of noise, linearity, offset, and
DIN
gain errors.
This pin is the data input pin. DIN is used along with
SCLK to send data to the device. Data on DIN are
Digital Interface
shifted into the device on the falling edge of SCLK.
The ADS1146/7/8 provide a standard SPI serial
The communication of this device is full-duplex in
communication interface plus a data ready signal
nature. The device monitors commands shifted in
(DRDY). Communication is full-duplex with the
even when data are being shifted out. Data that are
exception of a few limitations in regards to the RREG
present in the output shift register are shifted out
command and the RDATA command. These
when sending in a command. Therefore, it is
limitations are explained in detail in the SPI
important to make sure that whatever is being sent on
Commands section of this data sheet. For the basic
the DIN pin is valid when shifting out data. When no
serial interface timing characteristics, see Figure 1
command is to be sent to the device when reading
and Figure 2 of this document.
out data, the NOP command should be sent on DIN.
CS
DRDY
This pin is the chip select pin (active low). The CS pin
This pin is the data ready pin. The DRDY pin goes
activates SPI communication. CS must be low before
low to indicate a new conversion is complete, and the
data transactions and must stay low for the entire SPI
conversion result is stored in the conversion result
communication period. When CS is high, the
buffer. The SPI clock must be low in a short time
DOUT/DRDY pin enters a high-impedance state.
frame around the DRDY low transition (see Figure 2)
Therefore, reading and writing to the serial interface
so that the conversion result is loaded into both the
are ignored and the serial interface is reset. DRDY
result buffer and the output shift register. Therefore,
pin operation is independent of CS.
no commands should be issued during this time
Taking CS high deactivates only the SPI
frame if the conversion result is to be read out later.
communication with the device. Data conversion
This constraint applies only when CS is asserted.
continues and the DRDY signal can be monitored to
When CS is not asserted, SPI communication with
check if a new conversion result is ready. A master
other devices on the SPI bus does not affect loading
device monitoring the DRDY signal can select the
of the conversion result. After the DRDY pin goes
appropriate slave device by pulling the CS pin low.
low, it is forced high on the first falling edge of SCLK
(so that the DRDY pin can be polled for '0' instead of
waiting for a falling edge). If the DRDY pin is not
taken high after it falls low, a short high pulse is
created on it to indicate the next data are ready.
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