Datasheet

SCLK
DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[1] DOUT[0]
DIN[0] DIN[7] DIN[6] DIN[5] DIN[4] DIN[1] DIN[0]
CS
DOUT/
(1)
DRDY
DIN
t
CSSC
t
DIST
t
DIHD
t
SCLK
t
SCCS
t
CSDO
t
DOPD
t
SPWL
t
SPWH
t
DOHD
t
CSPW
SCLK
(3)
1 2 3 87654
DRDY
t
STD
t
DTS
t
PWH
ADS1146
ADS1147
ADS1148
SBAS453F –JULY 2009–REVISED APRIL 2012 www.ti.com
TIMING DIAGRAMS
Figure 1. Serial Interface Timing
Timing Characteristics for Figure 1
(1)
SYMBOL DESCRIPTION MIN MAX UNIT
t
CSSC
CS low to first SCLK high (set up time) 10 ns
t
SCCS
SCLK low to CS high (hold time) 7 t
OSC
(2)
t
DIST
DIN set up time 5 ns
t
DIHD
DIN hold time 5 ns
t
DOPD
SCLK rising edge to new data valid 50
(3)
ns
t
DOHD
DOUT hold time 0 ns
500 ns
t
SCLK
SCLK period
64 conversions
t
SPWH
SCLK pulse width high 0.25 0.75 t
SCLK
t
SPWL
SCLK pulse width low 0.25 0.75 t
SCLK
t
CSDO
CS high to DOUT high impedance 10 ns
t
CSPW
Chip Select high pulse width 5 t
OSC
(1) DRDY MODE bit = 0.
(2) t
OSC
= 1/f
CLK
. The default clock frequency f
CLK
= 4.096MHz.
(3) For DVDD > 3.6V, t
DOPD
= 180ns.
Figure 2. SPI Interface Timing to Allow Conversion Result Loading
(4)(5)
Timing Characteristics for Figure 2
SYMBOL DESCRIPTION MIN MAX UNIT
t
PWH
DRDY pulse width high 3 t
OSC
t
S TD
SCLK low prior to DRDY low 5 t
OSC
t
DTS
DRDY falling edge to SCLK rising edge 1/f
CLK
ns
(4) This timing diagram is applicable only when the CS pin is low. SCLK need not be low during t
STD
when CS is high.
(5) SCLK should only be sent in multiples of eight during partial retrieval of output data.
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