Datasheet

AbruptChangeinV
IN
V
IN
DRDY/DOUT
Startof
Conversion
1stConversion;
includes
unsettledV .
IN
2ndConversion;
V settled,but
IN
digitalfilter
unsettled.
3rdConversion;
V settled,but
IN
digitalfilter
unsettled.
4thConversion;
V settled,but
IN
digitalfilter
unsettled.
5thConversion;
V anddigital
IN
filterboth
settled.
Conversion
Time
ADS1131
www.ti.com
SBAS449C JULY 2009REVISED OCTOBER 2013
Table 1. Data Rate Settings
SETTLING TIME
SPEED PIN DATA RATE
Fast changes in the input signal require time to settle.
0 10SPS
For example, an external multiplexer in front of the
ADS1131 can generate abrupt changes in input
1 80SPS
voltage by simply switching the multiplexer input
channels. These sorts of changes in the input require
DATA FORMAT
four data conversion cycles to settle. When
The ADS1131 outputs 18 bits of data in binary twos
continuously converting, five readings may be
complement format. The least significant bit (LSB)
necessary in order to settle the data. If the change in
has a weight of (0.5V
REF
/64)(2
17
1). The positive
input occurs in the middle of the first conversion, four
full-scale input produces an output code of 1FFFFh
more full conversions of the fully-settled input are
and the negative full-scale input produces an output
required to obtain fully-settled data. Discard the first
code of 20000h. The output clips at these codes for
four readings because they contain only partially-
signals exceeding full-scale. Table 2 summarizes the
settled data. Figure 5 illustrates the settling time for
ideal output codes for different input signals.
the ADS1131.
Table 2. Ideal Output Code vs Input Signal
DATA RATE
INPUT SIGNAL V
IN
The ADS1131 data rate is set by the SPEED pin, as
(AINP AINN) IDEAL OUTPUT
shown in Table 1. When SPEED is low, the data rate
+0.5V
REF
/64 1FFFFh
is nominally 10SPS. This data rate provides the
00001h
(+0.5V
REF
/64)/(2
17
1)
lowest noise, and also has excellent rejection of both
0 00000h
50Hz and 60Hz line-cycle interference. For
applications requiring fast data rates, setting SPEED
3FFFFh
(–0.5V
REF
/64)/(2
17
1)
high selects a data rate of nominally 80SPS.
–0.5V
REF
/64 20000h
1. Excludes effects of noise, INL, offset, and gain
errors.
Figure 5. Settling Time in Continuous Conversion Mode
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: ADS1131