Datasheet

DRDY/DOUT 17 16
15
1 18
0
LSBMSB
Data
DataReady
SCLK
t
DS
t
CONV
t
SCLK
t
PD
NewDataReady
t
SCLK
t
HT
t
UPDATE
ADS1131
SBAS449C –JULY 2009–REVISED OCTOBER 2013 www.ti.com
DATA READY/DATA OUTPUT (DRDY/DOUT) DATA RETRIEVAL
This digital output pin serves two purposes. First, it The ADS1131 continuously converts the analog input
indicates when new data are ready by going low. signal. To retrieve data, wait until DRDY/DOUT goes
Afterwards, on the first rising edge of SCLK, the low, as shown in Figure 6. After DRDY/DOUT goes
DRDY/DOUT pin changes function and begins low, begin shifting out the data by applying SCLKs.
outputting the conversion data, most significant bit Data are shifted out MSB first. It is not required to
(MSB) first. Data are shifted out on each subsequent shift out all 18 bits of data, but the data must be
SCLK rising edge. After all 18 bits have been retrieved before new data are updated (within t
CONV
)
retrieved, the pin can be forced high with an or else the data will be overwritten. Avoid data
additional SCLK. It then stays high until new data are retrieval during the update period (t
UPDATE
). If only 18
ready. This configuration is useful when polling on the SCLKs have been applied, DRDY/DOUT remains at
status of DRDY/DOUT to determine when to begin the state of the last bit shifted out until it is taken high
data retrieval. (see t
UPDATE
), indicating that new data are being
updated. To avoid having DRDY/DOUT remain in the
state of the last bit, the 19th SCLK can be applied to
SERIAL CLOCK INPUT (SCLK)
force DRDY/DOUT high, as shown in Figure 7. This
This digital input shifts serial data out with each rising
technique is useful when a host controlling the device
edge. This input has built-in hysteresis, but care
is polling DRDY/DOUT to determine when data are
should still be taken to ensure a clean signal. Glitches
ready.
or slow-rising signals can cause unwanted additional
shifting. For this reason, it is best to make sure the
rise and fall times of SCLK are both less than 50ns.
Figure 6. 18-Bit Data Retrieval Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
DS
DRDY/DOUT low to first SCLK rising edge 0 ns
t
SCLK
SCLK positive or negative pulse width 100 ns
t
PD
(1)
SCLK rising edge to new data bit valid: propagation delay 50 ns
t
HT
(1)
SCLK rising edge to old data bit valid: hold time 20 ns
t
UPDATE
Data updating: no readback allowed 90 μs
SPEED = 1 12.5 ms
t
CONV
Conversion time (1/data rate)
SPEED = 0 100 ms
(1) Minimum required from simulation.
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