Datasheet

5
10
1
2
3
4
SCLK
CS
GND
AIN0
AIN1
DIN
9
8
7
6
DOUT/DRDY
VDD
AIN3
AIN2
1
2
3
4
5
10
9
8
7
6
SCLK
GND
AIN0
AIN1
DIN
VDD
AIN3
AIN2
CS
DOUT/DRDY
ADS1118
www.ti.com SBAS457D –OCTOBER 2010–REVISED OCTOBER 2013
PIN CONFIGURATIONS
RUG PACKAGE
DGS PACKAGE
QFN-10
MSOP-10
(TOP VIEW)
(TOP VIEW)
PIN DESCRIPTIONS
PIN # PIN NAME FUNCTION DESCRIPTION
1 SCLK Digital input Serial clock input
2 CS Digital input Chip select; active low
3 GND Analog Ground
4 AIN0 Analog input Differential channel 1: positive input or single-ended channel 1 input
5 AIN1 Analog input Differential channel 1: negative input or single-ended channel 2 input
6 AIN2 Analog input Differential channel 2: positive input or single-ended channel 3 input
7 AIN3 Analog input Differential channel 2: negative input or single-ended channel 4 input
8 VDD Analog Power supply: 2.0 V to 5.5 V
9 DOUT/DRDY Digital output Serial data out combined with data ready; active low
10 DIN Digital input Serial data input
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