Datasheet

9
8
7
6
1
2
3
4
10
5
SCLK
DIN
DOUT
CS
1
CS
2
DIN
DOUT/DRDY
VDD
AIN3
AIN2
AIN1
AIN0
GND
CS
SCLK
9
8
7
6
1
2
3
4
10
5
DIN
DOUT/DRDY
VDD
AIN3
AIN2
AIN1
AIN0
GND
CS
SCLK
Device
Device
Microcontroller or
Microprocessor
ADS1118
www.ti.com SBAS457D –OCTOBER 2010–REVISED OCTOBER 2013
CONNECTING MULTIPLE DEVICES
Connecting multiple ADS1118s to a single bus is simple. SCLK, DIN, and DOUT/DRDY can be safely shared by
using a dedicated chip-select (CS) for each SPI-enabled device. By default, when CS goes high for the
ADS1118, DOUT/DRDY is pulled up to the supply of the ADS1118 by a weak 400 kΩ resistor. This feature is
intended to prevent DOUT/DRDY from floating near mid-rail and causing excess current leakage on a
microcontroller input. If the PULL_UP_EN bit in the Config register is set to '0', the DOUT/DRDY pin enters a 3-
state mode when CS transitions high. The ADS1118 cannot issue a data ready pulse on DOUT/DRDY when CS
is high. In order to evaluate when a new conversion is ready from the ADS1118 when using multiple devices, the
master can periodically drop CS to the ADS1118. When CS goes low, the DOUT/DRDY pin immediately drives
either high or low. If the DOUT/DRDY line drives low on a low CS, new data are currently available for clocking
out at any time. If the DOUT/DRDY line drives high, no new data are available and the ADS1118 returns the last
read conversion result. Valid data can be retrieved from the ADS1118 at anytime without concern of data
corruption. If a new conversion becomes available during data transmission, it is not available for readback until
a new SPI transmission is initiated.
NOTE: Power and input connections omitted for clarity.
Figure 49. Connecting Multiple ADS1118s
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Product Folder Links: ADS1118