Datasheet

CS
SCLK
DOUT/DRDY
DIN
Hi-Z
1 9
DATA MSB DATA LSB
CONFIG MSB CONFIG LSB
1 9
DATA MSB DATA LSB
CONFIG MSB CONFIG LSB
ADS1118
SBAS457D –OCTOBER 2010–REVISED OCTOBER 2013 www.ti.com
16-Bit Data Transmission Cycle
If Config register data are not required to be readback, the ADS1118 conversion data can also be clocked out in
a short 16-bit data transmission cycle, as shown in Figure 46. Therefore, CS must be taken high after the 16th
SCLK cycle. Taking CS high resets the SPI interface. The next time CS is taken low, data transmission starts
with the currently buffered conversion result on the first SCLK rising edge. If DOUT/DRDY is low when data
retrieval starts, the conversion buffer is already updated with a new result. Otherwise, if DOUT/DRDY is high, the
same result from the previous data transmission cycle is read.
Figure 46. 16-Bit Data Transmission Cycle
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