Datasheet

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SBAS282D − JUNE 2003 − REVISED MARCH 2004
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9
When a master has finished communicating with a slave,
it may issue a STOP condition. When a STOP condition is
issued, the bus becomes idle again. A master may also
issue another START condition. When a START condition
is issued while the bus is active, it is called a repeated
START condition.
A timing diagram for an ADS1112 I
2
C transaction is shown
in Figure 1. The parameters for this diagram are given in
Table 3.
SERIAL BUS ADDRESS
To program the ADS1112, the master must first address
slave devices via a slave address byte. The slave address
byte consists of seven address bits, and a direction bit
indicating the intent of executing a read or write operation.
The ADS1112 features two address pins, A0 and A1, that
set the I
2
C address. These pins can be set to a logic low,
logic high, or left unconnected (floating), allowing eight
addresses to be selected with only two pins as shown in
Table 4. The state of pins A0 and A1 is sampled on
power-up or after an I
2
C general call, and should be set
prior to any activity on the interface.
I
2
C GENERAL CALL
The ADS1112 responds to the I
2
C General Call address
(0000000) if the eighth bit is 0. The device will
acknowledge the General Call address and respond to
commands in the second byte. If the second byte is
00000100 (04h), the ADS1112 will latch the status of the
address pins, A0 and A1, but not perform a reset. If the
second byte is 00000110 (06h), the ADS1112 will latch the
status of the address pins and reset the internal registers.
Figure 1. I
2
C Timing Diagram
FAST MODE HIGH-SPEED MODE
PARAMETER
MIN MAX MIN MAX
UNITS
SCLK operating frequency
t
(SCLK)
0.4 3.4 MHz
Bus free time between START and STOP condition
t
(BUF)
600 160 ns
Hold time after repeated START condition.
After this period, the first clock is generated.
t
(HDSTA)
600 160 ns
Repeated START condition setup time
t
(SUSTA)
600 160 ns
Stop condition setup time
t
(SUSTO)
600 160 ns
Data hold time
t
(HDDAT)
0 0 ns
Data setup time
t
(SUDAT)
100 10 ns
SCLK clock LOW period
t
(LOW)
1300 160 ns
SCLK clock HIGH period
t
(HIGH)
600 60 ns
Clock/data fall time
t
F
300 160 ns
Clock/data rise time
t
R
300 160 ns
Table 3. Timing Diagram Definitions