Datasheet

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SBAS282D − JUNE 2003 − REVISED MARCH 2004
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11
CONFIGURATION REGISTER
The 8-bit configuration register can be used to control the
ADS1112 operating mode, input selection, data rate, and
PGA settings. The configuration register format is shown
in Table 6. The default setting is 8C
H
.
BIT 7 6 5 4 3 2 1 0
NAME ST/DRDY INP1 INP0 SC DR1 DR0 PGA1 PGA0
DEFAULT 1 0 0 0 1 1 0 0
Table 6. Configuration Register
Bit 7: ST/DRDY
The meaning of the ST/DRDY bit depends on whether it is
being written to or read from.
In single conversion mode, writing a 1 to the ST/DRDY
bit
causes a conversion to start, and writing a 0 has no effect.
In continuous conversion mode, the ADS1112 ignores the
value written to ST/DRDY
.
When read, ST/DRDY
indicates whether the data in the
output register is new data. If ST/DRDY
is 0, the data just
read from the output register is new, and has not been read
before. If ST/DRDY
is 1, the data just read from the output
register has been read before.
The ADS1112 sets ST/DRDY
to 0 when it writes data into
the output register. It sets ST/DRDY
to 1 after any of the
bits in the configuration register have been read. (Note that
the read value of the bit is independent of the value written
to this bit.)
In continuous-conversion mode, use ST/DRDY
to
determine when new conversion data is ready. If
ST/DRDY
is 1, the data in the output register has already
been read, and is not new. If it is 0, the data in the output
register is new, and has not yet been read.
In single-conversion mode, use ST/DRDY to determine
when a conversion has completed. If ST/DRDY
is 1, the
output register data is old, and the conversion is still in
process; if it is 0, the output register data is the result of the
new conversion.
Note that the output register is returned from the ADS1112
before the configuration register. The state of the
ST/DRDY
bit applies to the data just read from the output
register, and not to the data from the next read operation.
Bits 6-5: INP
INP controls which two of the four analog inputs are used
to measure data in the ADC. This is shown in Table 7. By
selecting these bits, the ADS1112 can be used to measure
two differential channels or three single ended channels
referenced to AIN3.
INP1 INP0 V
IN+
V
IN−
0
(1)
0
(1)
AIN0 AIN1
0 1 AIN2 AIN3
1 0 AIN0 AIN3
1 1 AIN1 AIN3
(1)
Default setting.
Table 7. INP Bits.
Bit 4: SC
SC controls whether the ADS1112 is in continuous
conversion or single conversion mode. When SC is 1, the
ADS1112 is in single conversion mode; when SC is 0, it is
in continuous conversion mode. The default setting is 0.
Bits 3-2: DR
Bits 3 and 2 control the ADS1112 data rate, as shown in
Table 8.
DR1 DR0 DATA RATE RESOLUTION
0 0 240SPS 12 Bits
0 1 60SPS 14 Bits
1 0 30SPS 15 Bits
1
(1)
1
(1)
15SPS
(1)
16 Bits
(1)
(1)
Default setting.
Table 8. INP Bits.
Bits 1-0: PGA
Bits 1 and 0 control the ADS1112 gain setting, as shown
in Table 9.
PGA1 PGA0 GAIN
0
(1)
0
(1)
1
(1)
0 1 2
1 0 4
1 1 8
(1)
Default setting.
Table 9. PGA Bits