Datasheet

ADS1110
SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003
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9
When a master has finished communicating with a slave,
it may issue a STOP condition. When a STOP condition is
issued, the bus becomes idle again. A master may also
issue another START condition. When a START condition
is issued while the bus is active, it is called a repeated
START condition.
A timing diagram for an ADS1110 I
2
C transaction is shown
in Figure 1. The parameters for this diagram are given in
Table 3.
ADS1110 I
2
C ADDRESSES
The ADS1110 I
2
C address is 1001aaa, where aaa are bits
set at the factory. The ADS1110 is available in eight
different versions, each having a different I
2
C address. For
example, the ADS1110A0 has address 1001000, and the
ADS1110A3 has address 1001011. See the Ordering
Information table for a complete listing.
The I
2
C address is the only difference between the eight
variants. In all other respects, they operate identically.
Each variant of the ADS1110 is marked with EDx, where
x identifies the address variant. For example, the
ADS1110A0 is marked ED0, and the ADS1110A3 is
marked ED3. See the Package/Ordering Information table
for a complete listing.
I
2
C GENERAL CALL
The ADS1110 responds to a General Call Reset, which is
an address byte of 00h followed by a data byte of 06
H
. The
ADS1110 acknowledges both bytes.
On receiving a General Call Reset, the ADS1110 performs
a full internal reset, just as though it had been powered off
and then on. If a conversion is in process, it is interrupted;
the output register is set to zero, and the configuration
register is set to its default setting.
The ADS1110 always acknowledges the General Call
address byte of 00
H
, but it does not acknowledge any
General Call data bytes other than 04
H
or 06
H
.
Figure 1. I
2
C Timing Diagram
FAST MODE HIGH-SPEED MODE
PARAMETER
MIN MAX MIN MAX
UNITS
SCLK operating frequency
t
(SCLK)
0.4 3.4 MHz
Bus free time between START and STOP condition
t
(BUF)
600 160 ns
Hold time after repeated START condition.
After this period, the first clock is generated.
t
(HDSTA)
600 160 ns
Repeated START condition setup time
t
(SUSTA)
600 160 ns
Stop condition setup time
t
(SUSTO)
600 160 ns
Data hold time
t
(HDDAT)
0 0 ns
Data setup time
t
(SUDAT)
100 10 ns
SCLK clock LOW period
t
(LOW)
1300 160 ns
SCLK clock HIGH period
t
(HIGH)
600 60 ns
Clock/data fall time
t
F
300 160 ns
Clock/data rise time
t
R
300 160 ns
Table 3. Timing Diagram Definitions