Datasheet

ADS1110
SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003
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8
USING THE ADS1110
OPERATING MODES
The ADS1110 operates in one of two modes: continuous
conversion or single conversion.
In continuous conversion mode, the ADS1110 continuous-
ly performs conversions. Once a conversion has been
completed, the ADS1110 places the result in the output
register and immediately begins another conversion.
In single conversion mode, the ADS1110 waits until the
ST/DRDY
bit in the conversion register is set to 1. When
this happens, the ADS1110 powers up and performs a
single conversion. After the conversion completes, the
ADS1110 places the result in the output register, resets the
ST/DRDY
bit to 0, and powers down. Writing a 1 to
ST/DRDY
while a conversion is in progress has no effect.
When switched from continuous conversion mode to
single conversion mode, the ADS1110 completes the
current conversion, resets the ST/DRDY
bit to 0, and
powers down.
RESET AND POWER−UP
When the ADS1110 powers up, it automatically performs
a reset. As part of the reset, the ADS1110 sets all of the bits
in the configuration register to their default settings.
The ADS1110 responds to the I
2
C General Call Reset
command. When the ADS1110 receives a General Call
Reset, it performs an internal reset, exactly as though it
had just been powered on.
I
2
C INTERFACE
The ADS1110 communicates through an I
2
C
(inter-integrated circuit) interface. I
2
C is a two-wire
open-drain interface supporting multiple devices and
masters on a single bus. Devices on the I
2
C bus only drive
the bus lines LOW by connecting them to ground; they
never drive the bus lines HIGH. Instead, the bus wires are
pulled HIGH by pull-up resistors, so the bus wires are
HIGH when no device is driving them LOW. This way, two
devices cannot conflict; if two devices drive the bus
simultaneously, there is no driver contention.
Communication on the I
2
C bus always takes place
between two devices, one acting as the master and the
other acting as the slave. Both masters and slaves can
read and write, but slaves can only do so under the
direction of the master. Some I
2
C devices can act as
masters or slaves, but the ADS1110 can only act as a slave
device.
An I
2
C bus consists of two lines, SDA and SCL. SDA
carries data; SCL provides the clock. All data is
transmitted across the I
2
C bus in groups of eight bits. To
send a bit on the I
2
C bus, the SDA line is driven to the
appropriate level while SCL is LOW (a LOW on SDA
indicates the bit is zero; a HIGH indicates the bit is one).
Once the SDA line has settled, the SCL line is brought
HIGH, then LOW. This pulse on SCL clocks the SDA bit
into the receiver’s shift register.
The I
2
C bus is bidirectional: the SDA line is used both for
transmitting and receiving data. When a master reads from
a slave, the slave drives the data line; when a master
sends to a slave, the master drives the data line. The
master always drives the clock line. The ADS1110 never
drives SCL, because it cannot act as a master. On the
ADS1110, SCL is an input only.
Most of the time the bus is idle, no communication is taking
place, and both lines are HIGH. When communication is
taking place, the bus is active. Only master devices can
start a communication. They do this by causing a START
condition on the bus. Normally, the data line is only allowed
to change state while the clock line is LOW. If the data line
changes state while the clock line is HIGH, it is either a
START condition or its counterpart, a STOP condition. A
START condition is when the clock line is HIGH and the
data line goes from HIGH to LOW. A STOP condition is
when the clock line is HIGH and the data line goes from
LOW to HIGH.
After the master issues a START condition, it sends a byte
that indicates which slave device it wants to communicate
with. This byte is called the address byte. Each device on
an I
2
C bus has a unique 7-bit address to which it responds.
(Slaves can also have 10-bit addresses; see the I
2
C
specification for details.) The master sends an address in
the address byte, together with a bit that indicates whether
it wishes to read from or write to the slave device.
Every byte transmitted on the I
2
C bus, whether it is
address or data, is acknowledged with an acknowledge
bit. When a master has finished sending a byte (eight data
bits) to a slave, it stops driving SDA and waits for the slave
to acknowledge the byte. The slave acknowledges the
byte by pulling SDA LOW. The master then sends a clock
pulse to clock the acknowledge bit. Similarly, when a
master has finished reading a byte, it pulls SDA LOW to
acknowledge this to the slave. It then sends a clock pulse
to clock the bit. (Remember that the master always drives
the clock line.)
A not-acknowledge is performed by simply leaving SDA
HIGH during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it,
it will receive a not−acknowledge because no device is
present at that address to pull the line LOW.