Datasheet

ADS1110
SBAS276A − MARCH 2003 − REVISED NOVEMBER 2003
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6
TYPICAL CHARACTERISTICS (continued)
At T
A
= 25°C and V
DD
= 5V, unless otherwise noted.
THEORY OF OPERATION
The ADS1110 is a fully differential, 16-bit, self-calibrating,
delta-sigma A/D converter. Extremely easy to design with
and configure, the ADS1110 allows precise measure-
ments to be obtained with a minimum of effort.
The ADS1110 consists of a delta-sigma A/D converter
core with adjustable gain, a 2.048V reference, a clock os-
cillator, and an I
2
C interface. Each of these blocks are de-
scribed in detail in the sections that follow.
ANALOG-TO-DIGITAL CONVERTER
The ADS1110 A/D converter core consists of a differential
switched-capacitor delta-sigma modulator followed by a
digital filter. The modulator measures the voltage differ-
ence between the positive and negative analog inputs and
compares it to a reference voltage, which, in the ADS1110,
is 2.048V. The digital filter receives a high-speed bitstream
from the modulator and outputs a code, which is a number
proportional to the input voltage.
VOLTAGE REFERENCE
The ADS1110 contains an onboard 2.048V voltage refer-
ence. This reference is always used as the A/D converter’s
voltage reference; an external reference cannot be con-
nected. The ADS1110’s voltage reference is internal only,
and cannot be measured directly or used by external cir-
cuitry.
The onboard reference’s specifications are part of the
ADS1110’s overall gain and drift specifications. The con-
verter’s drift and gain error specifications reflect the perfor-
mance of the onboard reference as well as the perfor-
mance of the A/D converter core. There are no separate
specifications for the onboard reference itself.
OUTPUT CODE CALCULATION
The output code is a scalar value that is, except for clip-
ping, proportional to the voltage difference between the
two analog inputs. The output code is confined to a finite
range of numbers; this range depends on the number of
bits needed to represent the code. The number of bits
needed to represent the output code for the ADS1110 de-
pends on the data rate, as shown in Table 1.
DATA RATE
NUMBER OF
BITS
MINIMUM
CODE
MAXIMUM
CODE
15SPS 16 −32,768 32,767
30SPS 15 −16,384 16,383
60SPS 14 −8192 8191
240SPS 12 −2048 2047
Table 1. Minimum and Maximum Codes
For a minimum output code of Min Code, gain setting of
PGA, and positive and negative input voltages of V
IN+
and
V
IN−
, the output code is given by the expression:
Output Code + −1 Min Code PGA
(V
IN)
) * (V
IN*
)
2.048V
In the previous expression, it is important to note that the
negated minimum output code is used. The ADS1110
outputs codes in binary two’s complement format, so the
absolute values of the minima and maxima are not the
same; the maximum n−bit code is 2
n−1
− 1, while the
minimum n−bit code is −1 × 2
n−1
.