Datasheet

ADS1100
9
SBAS239B
www.ti.com
I
2
C GENERAL CALL
The ADS1100 responds to General Call Reset, which is an
address byte of 00
H
followed by a data byte of 06
H
. The
ADS1100 acknowledges both bytes.
On receiving a General Call Reset, the ADS1100 performs a
full internal reset, just as though it had been powered off and
then on. If a conversion is in process, it is interrupted; the
output register is set to zero, and the configuration register is
set to its default setting.
The ADS1100 always acknowledges the General Call ad-
dress byte of 00
H
, but it does not acknowledge any General
Call data bytes other than 04
H
or 06
H
.
I
2
C DATA RATES
The I
2
C bus operates in one of three speed modes: Stan-
dard, which allows a clock frequency of up to 100kHz; Fast,
which allows a clock frequency of up to 400kHz; and High-
speed mode (also called Hs mode), which allows a clock
frequency of up to 3.4MHz. The ADS1100 is fully compatible
with all three modes.
No special action needs to be taken to use the ADS1100 in
Standard or Fast modes, but High-speed mode must be
activated. To activate High-speed mode, send a special
address byte of 00001XXX following the start condition,
where the XXX bits are unique to the Hs-capable master.
This byte is called the Hs master code. (Note that this is
different from normal address bytes: the low bit does not
indicate read/write status.) The ADS1100 will not acknowl-
edge this byte; the I
2
C specification prohibits acknowledg-
ment of the Hs master code. On receiving a master code, the
ADS1100 will switch on its High-speed mode filters, and will
communicate at up to 3.4MHz. The ADS1100 switches out of
Hs mode with the next stop condition.
For more information on High-speed mode, consult the I
2
C
specification.
REGISTERS
The ADS1100 has two registers that are accessible via its I
2
C
port. The output register contains the result of the last conver-
sion; the configuration register allows you to change the
ADS1100’s operating mode and query the status of the device.
OUTPUT REGISTER
The 16-bit output register contains the result of the last
conversion in binary two’s complement format. Following
reset or power-up, the output register is cleared to zero; it
remains zero until the first conversion is completed. There-
fore, if you read the ADS1100 just after reset or power-up,
you will read zero from the output register.
The output register’s format is shown in Table IV.
CONFIGURATION REGISTER
You can use the 8-bit configuration register to control the
ADS1100’s operating mode, data rate, and PGA settings.
The configuration register’s format is shown in Table V. The
default setting is 8CH.
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNITS
SCLK Operating Frequency f
(SCLK)
0.4 3.4 MHz
Bus Free Time Between STOP and START Condition t
(BUF)
600 160 ns
Hold Time After Repeated START Condition. t
(HDSTA)
600 160 ns
After this period, the first clock is generated.
Repeated START Condition Setup Time t
(SUSTA)
600 160 ns
STOP Condition Setup Time t
(SUSTO)
600 160 ns
Data Hold Time t
(HDDAT)
00 ns
Data Setup Time t
(SUDAT)
100 10 ns
SCLK Clock LOW Period t
(LOW)
1300 160 ns
SCLK Clock HIGH Period t
(HIGH)
600 60 ns
Clock/Data Fall Time t
F
300 160 ns
Clock/Data Rise Time t
R
300 160 ns
TABLE III. Timing Diagram Definitions.
BIT 1514131211109876543210
NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TABLE IV. Output Register.
BIT 7 654321 0
NAME ST/BSY 0 0 SC DR1 DR0 PGA1 PGA0
TABLE V. Configuration Register.
Bit 7: ST/BSY
The meaning of the ST/BSY bit depends on whether it is
being written to or read from.
In single conversion mode, writing a 1 to the ST/BSY bit
causes a conversion to start, and writing a 0 has no effect.
In continuous conversion mode, the ADS1100 ignores the
value written to ST/BSY.