Datasheet

ADS1100
10
SBAS239B
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When read in single conversion mode, ST/BSY indicates whether
the A/D converter is busy taking a conversion. If ST/BSY is read
as 1, the A/D converter is busy, and a conversion is taking
place; if 0, no conversion is taking place, and the result of the
last conversion is available in the output register.
In continuous mode, ST/BSY is always read as 1.
Bits 6-5: Reserved
Bits 6 and 5 must be set to zero.
Bit 4: SC
SC controls whether the ADS1100 is in continuous conver-
sion or single conversion mode. When SC is 1, the ADS1100
is in single conversion mode; when SC is 0, the ADS1100 is
in continuous conversion mode. The default setting is 0.
Bits 3-2: DR
Bits 3 and 2 control the ADS1100’s data rate, as shown in
Table VI.
Bits 1-0: PGA
Bits 1 and 0 control the ADS1100’s gain setting, as shown in
Table VII.
READING FROM THE ADS1100
You can read the output register and the contents of the
configuration register from the ADS1100. To do this, address
the ADS1100 for reading, and read three bytes from the
device. The first two bytes are the output register’s contents;
the third byte is the configuration register’s contents.
You do not always have to read three bytes from the
ADS1100. If you want only the contents of the output regis-
ter, read only two bytes.
Reading more than three bytes from the ADS1100 has no
effect. All of the bytes beginning with the fourth will be FF
H
.
See Figure 2 for a timing diagram of an ADS1100 read
operation.
WRITING TO THE ADS1100
You can write new contents into the configuration register
(you cannot change the contents of the output register). To
do this, address the ADS1100 for writing, and write one byte
to it. This byte is written into the configuration register.
Writing more than one byte to the ADS1100 has no effect.
The ADS1100 will ignore any bytes sent to it after the first
one, and it will only acknowledge the first byte.
See Figure 3 for a timing diagram of an ADS1100 write
operation.
DR1 DR0 DATA RATE
0 0 128SPS
0 1 32SPS
1 0 16SPS
1
(1)
1
(1)
8SPS
(1)
NOTE: (1) Default Setting.
TABLE VI. DR Bits.
PGA1 PGA0 GAIN
0
(1)
0
(1)
1
(1)
01 2
10 4
11 8
NOTE: (1) Default Setting.
TABLE VII. PGA Bits.