Datasheet

5
10
1
2
3
4
SCLK
CS
GND
AIN0
AIN1
DIN
9
8
7
6
DOUT/DRDY
VDD
AIN3
AIN2
1
2
3
4
5
10
9
8
7
6
SCLK
GND
AIN0
AIN1
DIN
VDD
AIN3
AIN2
CS
DOUT/DRDY
ADS1018
SBAS526B NOVEMBER 2012REVISED OCTOBER 2013
www.ti.com
PIN CONFIGURATIONS
RUG PACKAGE
DGS PACKAGE
QFN-10
MSOP-10
(Top View)
(Top View)
PIN DESCRIPTIONS
PIN NAME PIN NO. FUNCTION DESCRIPTION
AIN0 4 Analog input Differential channel 1: positive input or single-ended channel 1 input
AIN1 5 Analog input Differential channel 1: negative input or single-ended channel 2 input
AIN2 6 Analog input Differential channel 2: positive input or single-ended channel 3 input
AIN3 7 Analog input Differential channel 2: negative input or single-ended channel 4 input
CS 2 Digital input Chip select; active low
DIN 10 Digital input Serial data input
DOUT/DRDY 9 Digital output Serial data out combined with data ready; active low
GND 3 Analog Ground
SCLK 1 Digital input Serial clock input
VDD 8 Analog Power supply: 2.0 V to 5.5 V
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