Datasheet

SCLK
CS
DIN
DOUT
t
SCLK
t
CSSC
t
SPWH
t
DIHD
t
SPWL
t
CSDOZ
t
DOHD
t
DOPD
t
SCCS
t
SCSC
t
CSH
t
CSDOD
t
DIST
Hi-Z
Hi-Z
ADS1018
www.ti.com SBAS526B –NOVEMBER 2012–REVISED OCTOBER 2013
PARAMETER MEASUREMENT INFORMATION
SPI TIMING CHARACTERISTICS
Figure 1. Serial Interface Timing
TIMING REQUIREMENTS: SERIAL INTERFACE TIMING
(1)
PARAMETER MIN MAX UNIT
t
CSSC
CS low to first SCLK: setup time
(2)
100 ns
t
SCLK
SCLK period 250 ns
t
SPWH
SCLK pulse width: high 100 ns
100 ns
t
SPWL
SCLK pulse width: low
(3)
28 ms
t
DIST
Valid DIN to SCLK falling edge: setup time 50 ns
t
DIHD
Valid DIN to SCLK falling edge: hold time 50 ns
t
DOPD
SCLK rising edge to valid new DOUT: propagation delay
(4)
50 ns
t
DOHD
SCLK rising edge to DOUT invalid: hold time 0 ns
t
CSDOD
CS low to DOUT driven: propagation delay 100 ns
t
CSDOZ
CS high to DOUT Hi-Z: propagation delay 100 ns
t
CSH
CS high pulse 200 ns
t
SCCS
Final SCLK falling edge to CS high 100 ns
(1) At T
A
= –40°C to +125°C and VDD = 2.0 V to 5.5 V, unless otherwise noted.
(2) CS can be tied low.
(3) Holding SCLK low longer than 28 ms resets the SPI interface.
(4) DOUT load = 20 pF || 100 kΩ to GND.
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