Datasheet

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SBAS473C –MAY 2009–REVISED OCTOBER 2009

Lo_thresh AND Hi_thresh REGISTERS register MSB to ‘0’. However, in all other cases, the

Hi_thresh register must be larger than the Lo_thresh

The upper and lower threshold values used by the

comparator are stored in two 16-bit registers. These

Table 10. When set to RDY mode, the ALERT/RDY

registers store values in the same format that the

pin outputs the state of the OS bit when in single-shot

output register displays values; that is, they are

mode and pulses when in continuous conversion

stored in twos complement format. Because it is

mode. Bits [3:0] in both the Lo_thresh and Hi_thresh

implemented as a digital comparator, special

registers have no effect on the comparator level

attention should be taken to readjust values

thresholds. These bits should be considered as don't

whenever PGA settings are changed.

care bits.

A secondary conversion ready function of the

comparator output pin can be realized by setting the

Hi_thresh register MSB to '1' and the Lo_thresh

Table 10. Lo_thresh and Hi_thresh Registers

BIT 15 14 13 12 11 10 9 8

NAME Lo_thresh11 Lo_thresh10 Lo_thresh9 Lo_thresh8 Lo_thresh7 Lo_thresh6 Lo_thresh5 Lo_thresh4

blank

BIT 7 6 5 4 3 2 1 0

NAME Lo_thresh3 Lo_thresh2 Lo_thresh1 Lo_thresh0 0 0 0 0

BIT 15 14 13 12 11 10 9 8

NAME Hi_thresh11 Hi_thresh10 Hi_thresh9 Hi_thresh8 Hi_thresh7 Hi_thresh6 Hi_thresh5 Hi_thresh4

blank

BIT 7 6 5 4 3 2 1 0

NAME Hi_thresh3 Hi_thresh2 Hi_thresh1 Hi_thresh0 1 1 1 1

Lo_thresh default = 8000h.

Hi_thresh default = 7FFFh.

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