Datasheet

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ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
An I
2
C bus consists of two lines, SDA and SCL. SDA Every byte transmitted on the I
2
C bus, whether it be
carries data; SCL provides the clock. All data is address or data, is acknowledged with an
transmitted across the I
2
C bus in groups of eight bits. acknowledge bit. When a master has finished
To send a bit on the I
2
C bus, the SDA line is driven to sending a byte, eight data bits, to a slave, it stops
the bit level while SCL is low (a Low on SDA driving SDA and waits for the slave to acknowledge
indicates the bit is '0'; a High indicates the bit is '1'). the byte. The slave acknowledges the byte by pulling
Once the SDA line has settled, the SCL line is SDA low. The master then sends a clock pulse to
brought high, then low. This pulse on SCL clocks the clock the acknowledge bit. Similarly, when a master
SDA bit into the receiver shift register. has finished reading a byte, it pulls SDA low to
acknowledge to the slave that it has finished reading
The I
2
C bus is bidirectional: the SDA line is used both
the byte. It then sends a clock pulse to clock the bit.
for transmitting and receiving data. When a master
(Remember that the master always drives the clock
reads from a slave, the slave drives the data line;
line.)
when a master sends to a slave, the master drives
the data line. The master always drives the clock line. A not-acknowledge is performed by simply leaving
The ADS1000 never drives SCL, because it cannot SDA high during an acknowledge cycle. If a device is
act as a master. On the ADS1000, SCL is an input not present on the bus, and the master attempts to
only. address it, it will receive a not-acknowledge because
no device is present at that address to pull the line
Most of the time the bus is idle, no communication
low.
takes place, and both lines are high. When
communication takes place, the bus is active. Only When a master has finished communicating with a
master devices can start a communication. They do slave, it may issue a stop condition. When a stop
this by causing a start condition on the bus. Normally, condition is issued, the bus becomes idle again. A
the data line is only allowed to change state while the master may also issue another start condition. When
clock line is low. If the data line changes state while a start condition is issued while the bus is active, it is
the clock line is high, it is either a start condition or its called a repeated start condition.
counterpart, a stop condition. A start condition is
A timing diagram for an ADS1000 I
2
C transaction is
when the clock line is high and the data line goes
shown in Figure 6 . Table 1 gives the parameters for
from high to low. A stop condition is when the clock
this diagram.
line is high and the data line goes from low to high.
After the master issues a start condition, it sends a
byte that indicates with which slave device it wants to
communicate. This byte is called the address byte.
Each device on an I
2
C bus has a unique 7-bit
address to which it responds. (Slaves can also have
10-bit addresses; see the I
2
C specification for
details.) The master sends an address in the address
byte, together with a bit that indicates whether it
wishes to read from or write to the slave device.
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