Datasheet

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THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTER
RESET AND POWER-UP
OUTPUT CODE CALCULATION
I
2
C INTERFACE
Output Code + 2048(PGA)
ǒ
V
IN)
*V
IN
−
V
DD
Ǔ
CLOCK GENERATOR
USING THE ADS1000
OPERATING MODES
ADS1000
SBAS357A – SEPTEMBER 2006 – REVISED OCTOBER 2007
conversion has been completed, the ADS1000 places
The ADS1000 is a fully differential, 12-bit A/D
the result in the output register, and immediately
converter. The ADS1000 allows users to obtain
begins another conversion. When the ADS1000 is in
precise measurements with a minimum of effort, and
continuous conversion mode, the ST/BSY bit in the
the device is extremely easy to design with and
configuration register always reads '1'.
configure.
In single conversion mode, the ADS1000 waits until
The ADS1000 consists of an A/D converter core with
the ST/BSY bit in the conversion register is set to '1'.
adjustable gain, a clock generator, and an I
2
C
When this happens, the ADS1000 powers up and
interface. Each of these blocks are described in detail
performs a single conversion. After the conversion
in the sections that follow.
completes, the ADS1000 places the result in the
output register, resets the ST/BSY bit to '0' and
powers down. Writing a '1' to ST/BSY while a
conversion is in progress has no effect.
The ADS1000 uses a switched-capacitor input stage.
To external circuitry, it looks roughly like a resistance.
When switching from continuous conversion mode to
The resistance value depends on the capacitor
single conversion mode, the ADS1000 will complete
values and the rate at which they are switched. The
the current conversion, reset the ST/BSY bit to '0' and
switching clock is generated by the onboard clock
power-down the device.
generator, so its frequency, nominally 275kHz, is
dependent on supply voltage and temperature. The
capacitor values depend on the PGA setting.
When the ADS1000 powers up, it automatically
The common-mode and differential input impedances
performs a reset. As part of the reset, the ADS1000
are different. For a gain setting of PGA, the
sets all of the bits in the configuration register to their
differential input impedance is typically 2.4M Ω /PGA.
respective default settings.
The common-mode impedance is typically 8M Ω .
The ADS1000 responds to the I
2
C General Call
Reset command. When the ADS1000 receives a
General Call Reset, it performs an internal reset,
exactly as though it had just been powered on.
The ADS1000 outputs codes in binary two ’ s
complement format. The output code is confined to
the range of numbers: – 2048 to 2047, and is given
by:
The ADS1000 communicates through an I
2
C
(Inter-Integrated Circuit) interface. The I
2
C interface is
a two-wire, open-drain interface supporting multiple
devices and masters on a single bus. Devices on the
I
2
C bus only drive the bus lines low, by connecting
them to ground; they never drive the bus lines high.
Instead, the bus wires are pulled high by pull-up
The ADS1000 features an onboard clock generator.
resistors, so the bus wires are high when no device is
The Typical Characteristics show variations in data
driving them low. This way, two devices cannot
rate over supply voltage and temperature. It is not
conflict; if two devices drive the bus simultaneously,
possible to operate the ADS1000 with an external
there is no driver contention.
clock.
Communication on the I
2
C bus always takes place
between two devices, one acting as the master and
the other acting as the slave. Both masters and
slaves can read and write, but slaves can only do so
under the direction of the master. Some I
2
C devices
The ADS1000 operates in one of two modes:
can act as masters or slaves, but the ADS1000 can
continuous conversion and single conversion.
only act as a slave device.
In continuous conversion mode, the ADS1000
continuously performs conversions. Once a
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