Datasheet

ADCS7476, ADCS7477, ADCS7478

www.ti.com

SNAS192F –APRIL 2003–REVISED MARCH 2013

Note that, even though the digital inputs are tolerant of up to +6.5V above GND, the digital outputs are only

capable of driving V

out. In addition, the digital input pins are not prone to latch-up; SCLK and CS may be

asserted before V

without any risk.

MODES OF OPERATION

The ADCS7476/77/78 has two possible modes of operation: NORMAL MODE, and SHUTDOWN MODE. The

ADCS7476/77/78 enters normal mode (and a conversion process is begun) when CS is pulled low. The device

will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or will

stay in normal mode if CS remains low. Once in shutdown mode, the device will stay there until CS is brought

low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade-off

throughput for power consumption.

NORMAL MODE

The best possible throughput is obtained by leaving the ADCS7476/77/78 in normal mode at all times, so there

are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the

10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS

low).

If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal

mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output

word).

Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles

have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought

high again before the start of the next conversion, which begins when CS is again brought low.

After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after t

QUIET

has

elapsed, by bringing CS low again.

SHUTDOWN MODE

Shutdown mode is appropriate for applications that either do not sample continuously, or are willing to trade

throughput for power consumption. When the ADCS7476/77/78 is in shutdown mode, all of the analog circuitry is

turned off.

To enter shutdown mode, a conversion must be interrupted by bringing CS back high anytime between the

second and tenth falling edges of SCLK, as shown in Figure 32. Once CS has been brought high in this manner,

the device will enter shutdown mode; the current conversion will be aborted and SDATA will enter TRI-STATE. If

CS is brought high before the second falling edge of SCLK, the device will not change mode; this is to avoid

accidentally changing mode as a result of noise on the CS line.

Figure 32. Entering Shutdown Mode

Product Folder Links: ADCS7476 ADCS7477 ADCS7478