Datasheet
ADC78H90
www.ti.com
SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
ADC78H90 Converter Electrical Characteristics
(1)
(continued)
The following specifications apply for AV
DD
= DV
DD
= +2.7V to 5.25V, AGND = DGND = 0V, f
SCLK
= 8 MHz, f
SAMPLE
= 500
KSPS, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Limits
Symbol Parameter Conditions Typical Units
(2)
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
2.7 V (min)
AV
DD
,
Analog and Digital Supply Voltages AV
DD
≥ DV
DD
DV
DD
5.25 V (max)
AV
DD
= DV
DD
= +4.75V to +5.25V,
1.65 2.3 mA (max)
f
SAMPLE
= 500 kSPS, f
IN
= 40 kHz
Total Supply Current, Normal Mode
(Operational, CS low)
AV
DD
= DV
DD
= +2.7V to +3.6V,
0.5 2.3 mA (max)
f
SAMPLE
= 500 kSPS, f
IN
= 40 kHz
I
A
+ I
D
AV
DD
= DV
DD
= +4.75V to +5.25V,
200 nA
f
SAMPLE
= 0 kSPS
Total Supply Current, Shutdown (CS
high)
AV
DD
= DV
DD
= +2.7V to +3.6V,
200 nA
f
SAMPLE
= 0 kSPS
\AV
DD
= DV
DD
= +4.75V to +5.25V 8.3 12 mW (max)
Power Consumption, Normal Mode
(Operational, CS low)
AV
DD
= DV
DD
= +2.7V to +3.6V 1.5 8.3 mW (max)
P
D
AV
DD
= DV
DD
= +4.75V to +5.25V 0.5 µW
Power Consumption, Shutdown (CS
high)
AV
DD
= DV
DD
= +2.7V to +3.6V 0.3 µW
AC ELECTRICAL CHARACTERISTICS
f
SCLK
Maximum Clock Frequency 8 MHz (min)
f
SMIN
Minimum Clock Frequency 50 kHz
f
S
Maximum Sample Rate 500 KSPS (min)
t
CONV
Conversion Time 13 SCLK cycles
40 % (min)
DC SCLK Duty Cycle 50
60 % (max)
t
ACQ
Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles
Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles
f
RATE
Throughput Rate 500 kSPS (min)
t
AD
Aperture Delay 4 ns
ADC78H90 Timing Specifications
The following specifications apply for AV
DD
= DV
DD
= +2.7V to 5.25V, AGND = DGND = 0V, f
SCLK
= 8 MHz, f
SAMPLE
= 500
KSPS, C
L
= 50 pF, Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Limits
Symbol Parameter Conditions Typical Units
(1)
Setup Time SCLK High to CS Falling
t
1a
(2)
10 ns (min)
Edge
Hold time SCLK Low to CS Falling
t
1b
(2)
10 ns (min)
Edge
t
2
Delay from CS Until DOUT active 30 ns (max)
Data Access Time after SCLK Falling
t
3
30 ns (max)
Edge
Data Setup Time Prior to SCLK Rising
t
4
10 ns (min)
Edge
t
5
Data Valid SCLK Hold Time 10 ns (min)
t
6
SCLK High Pulse Width 0.4 x t
SCLK
ns (min)
t
7
SCLK Low Pulse Width 0.4 x t
SCLK
ns (min)
CS Rising Edge to DOUT High-
t
8
20 ns (max)
Impedance
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t
1a
and t
1b
.
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