Datasheet

ADC78H90
www.ti.com SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
USING THE ADC78H90
Figure 3 and Figure 4 for the ADC78H90 are shown in Timing Diagrams. CS, chip select, initiates conversions
and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of
serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB
first. Data to be written to the ADC78H90's Control Register is placed on DIN, the serial data input pin. New data
is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when
CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a
power down state when CS is high.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out, MSB first. If there is more than one
conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising
edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK, where "N" must be an
integer.
When CS is brought high, SCLK is internally gated off. If SCLK is in a low state when CS goes high, the
subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is in a high state when CS goes high,
the ADC enters the track mode on the first falling edge of SCLK after the falling edge of CS.
During each conversion, data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS.
For each conversion, it is necessary to clock in the data indicating the input that is selected for the conversion
after the current one. See Table 1, Table 2, and Table 3.
If CS and SCLK go low simultaneously, it is the following rising edge of SCLK that is considered the first rising
edge for clocking data into DIN.
Table 1. Control Register Bits
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
Table 2. Control Register Bit Descriptions
Bit #: Symbol: Description
7, 6, 2, 1, 0 DONTC Don't care. The value of these bit do not affect the device.
5 ADD2 These three bits determine which input channel will be sampled and converted on the next falling
edge of CS. The mapping between codes and channels is shown in Table 3.
4 ADD1
3 ADD0
Table 3. Input Channel Selection
ADD2 ADD1 ADD0 Input Channel
0 0 0 AIN1 (Default)
0 0 1 AIN2
0 1 0 AIN3
0 1 1 AIN4
1 0 0 AIN5
1 0 1 AIN6
1 1 0 AIN7
1 1 1 AIN8
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