Datasheet
AIN1
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
AIN8
AV
DD
/2
AIN1
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
AV
DD
/2
SW2
AIN8
ADC78H90
SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
www.ti.com
APPLICATIONS INFORMATION
ADC78H90 OPERATION
The ADC78H90 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Simplified schematics of the ADC78H90 in both track and hold
operation are shown in Figure 21 and Figure 22, respectively. In Figure 21, the ADC78H90 is in track mode:
switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and
SW2 balances the comparator inputs. The ADC78H90 is in this state for the first three SCLK cycles after CS is
brought low.
There is no power-up delay or dummy conversions with the ADC78H90. The ADC is able to sample and convert
an input to full resolution in the first conversion immediately following power up. The first conversion result after
power up will be that of the first channel.
Figure 22 shows the ADC78H90 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC78H90 is in this state for the last thirteen SCLK cycles after
CS is brought low.
Figure 21. ADC78H90 in Track Mode
Figure 22. ADC78H90 in Hold Mode
The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of
16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is
clocked into the DIN pin to indicate the multiplexer address for the next conversion.
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