Datasheet
ADC78H89
www.ti.com
SNAS201D –APRIL 2003–REVISED MARCH 2013
ADC78H89 CONVERTER ELECTRICAL CHARACTERISTICS
(1)
(continued)
The following specifications apply for AV
DD
= DV
DD
= +2.7V to 5.25V, f
SCLK
= 8 MHz, f
SAMPLE
= 500 KSPS unless otherwise
noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits Units
(2)
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
(3)
2.7 V (min)
AV
DD
,
Analog and Digital Supply Voltages AV
DD
≥ DV
DD
DV
DD
5.25 V (max)
AV
DD
= DV
DD
= +4.75V to +5.25V,
1.65 2.3 mA (max)
f
SAMPLE
= 500 KSPS, f
IN
= 40 kHz
Total Supply Current, Normal Mode
(Operational, CS low)
AV
DD
= DV
DD
= +2.7V to +3.6V,
0.5 2.3 mA (max)
f
SAMPLE
= 500 KSPS, f
IN
= 40 kHz
I
DD
AV
DD
= DV
DD
= +4.75V to +5.25V,
0.1 µA
f
SAMPLE
= 0 KSPS
Total Supply Current, Shutdown (CS
high)
AV
DD
= DV
DD
= +2.7V to +3.6V,
0.1 µA
f
SAMPLE
= 0 KSPS
AV
DD
= DV
DD
= +4.75V to +5.25V 8.3 12 mW (max)
Power Consumption, Normal Mode
(Operational, CS low)
AV
DD
= DV
DD
= +2.7V to +3.6V 1.5 8.3 mW (max)
P
D
AV
DD
= DV
DD
= +4.75V to +5.25V 0.5 µW
Power Consumption, Shutdown (CS
high)
AV
DD
= DV
DD
= +2.7V to +3.6V 0.3 µW
AC ELECTRICAL CHARACTERISTICS
f
SCLK
Maximum Clock Frequency 8 MHz (max)
Minimum Clock Frequency 50 kHz
f
S
Maximum Sample Rate 500 KSPS (min)
t
CONV
Conversion Time 13 13 SCLK cycles
40 % (min)
DC Duty Cycle 50
60 % (max)
t
ACQ
Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles
Throughput Time Conversion Time + Acquisition Time 16 SCLK cycles
f
RATE
Throughput Rate 500 KSPS (min)
t
AD
Aperture Delay 4 ns
(3) Except power supply pins.
ADC78H89 TIMING SPECIFICATIONS
The following specifications apply for AV
DD
= DV
DD
= +2.7V to 5.25V, f
SCLK
= 8 MHz, C
L
= 50 pF, Boldface limits apply for
T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits Units
t
1a
SCLK High to CS Fall Setup Time See
(1)
10 ns (min)
t
1b
SCLK Low to CS Fall Hold Time See
(1)
10 ns (min)
t
2
Delay from CS Until DOUT TRI-STATE™ Disabled 30 ns (max)
t
3
Data Access Time after SCLK Falling Edge 30 ns (max)
t
4
Data Setup Time Prior to SCLK Rising Edge 10 ns (max)
t
5
Data Valid SCLK Hold Time 10 ns (max)
t
6
SCLK High Pulse Width 0.4 x t
SCLK
ns (min)
t
7
SCLK Low Pulse Width 0.4 x t
SCLK
ns (min)
t
8
CS Rising Edge to DOUT High-Impedance 20 ns (max)
(1) Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t
1a
and t
1b
.
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