Datasheet

ADC78H89

SNAS201D –APRIL 2003–REVISED MARCH 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Block Diagram

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

5 - 11 AIN1 to AIN7 Analog inputs. These signals can range from 0V to AV

This pin is not connected internally, and can be left floating, or tied to

2 NC

ground.

DIGITAL I/O

Digital clock input. The range of frequencies for this input is 50 kHz

16 SCLK to 8 MHz, with ensured performance at 8 MHz. This clock directly

controls the conversion and readout processes.

Digital data output. The output samples are clocked out of this pin on

15 DOUT

falling edges of the SCLK pin.

Digital data input. The ADC78H89's Control Register is loaded

14 DIN

through this pin on rising edges of the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins.

1 CS

Conversions continue as long as CS is held low.

POWER SUPPLY

Positive analog supply pin. This pin should be connected to a quiet

+2.7V to +5.25V source and bypassed to GND with 0.1 µF ceramic

3 AV

monolithic and 1 µF tantalum capacitors located within 1 cm of the

power pin.

Positive digital supply pin. This pin should be connected to a +2.7V

13 DV

to AV

supply, and bypassed to GND with a 0.1 µF ceramic

monolithic capacitor located within 1 cm of the power pin.

The ground return for both analog and digital supplies. These pins

are tied directly together internally, so must be connected to the

4, 12 GND

same potential. If any potential exists across these pins, large

currents will flow through the device.

Product Folder Links: ADC78H89