Datasheet

ADC78H89

SNAS201D –APRIL 2003–REVISED MARCH 2013

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The ADC78H89 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one

exception: the ADC78H89 automatically enters power-down mode between the 16th falling edge of a conversion

and the 1st falling edge of the subsequent conversion (see Figure 2).

The ADC78H89 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The

ADC78H89 will perform conversions continuously as long as CS is held low.

The user may trade off throughput for power consumption by simply performing fewer conversions per unit time.

The Power Consumption vs. Sample Rate curve in the Typical Performance Curves section shows the typical

power consumption of the ADC78H89 versus throughput. To calculate the power consumption, simply multiply

the fraction of time spent in the normal mode by the normal mode power consumption (8.3 mW with AV

= +3.6V, for example), and add the fraction of time spent in shutdown mode multiplied by the shutdown

mode power dissipation (0.3 mW with AV

= DV

= +3.6V).

Power Supply Noise Considerations

The charging of any output load capacitance requires current from the digital supply, DV

. The current pulses

required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If

these variations are large enough, they could cause degrade SNR and SINAD performance of the ADC.

Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply will be

coupled directly into the analog supply, causing greater performance degradation than noise on the digital

supply. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic

low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground

bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger is

the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into

the analog channel, degrading noise performance.

The first solution is to decouple the analog and digital supplies from each other, or use separate supplies for

them, to keep digital noise out of the analog supply. To keep noise out of the digital supply, keep the output load

capacitance as small as practical. If the load capacitance is greater than 25 pF, use a 100 Ω series resistor at

the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge

current of the output capacitance and improve noise performance.

Product Folder Links: ADC78H89