Datasheet

ADC78H89
SNAS201D –APRIL 2003–REVISED MARCH 2013 www.ti.com
APPLICATION INFORMATION
USING THE ADC78H89
An operational timing diagram and a serial interface timing diagram for the ADC78H89 are shown in the Timing
Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC78H89's
Control Register is placed on DIN, the serial data in pin.
The conversion process and serial data timing are controlled by the SCLK. Each conversion requires 16 SCLK
cycles to complete. Conversions are begun by bringing CS low. Several conversions can be executed
sequentially in a single serial frame, which is defined as the time between falling and rising edges of CS. If CS is
held low continuously, the ADC78H89 will perform conversions continuously.
Each time CS goes low, a conversion process is initiated simultaneously with a load of the Control Register. The
new contents of the Control Register will affect the next conversion. There is thus a one sample delay between
selecting a new input channel and observing the corresponding output.
Basic operation of the ADC78H89 begins with CS going low and initiating a conversion process and data
transfer. At this time the DOUT pin comes out of the high impedance state. The converter enters track mode at
the first falling edge of SCLK after CS is brought low, and begins to acquire the input signal. Acquisition of the
input signal continues during the first three SCLK cycles after the falling edge of CS. This acquisition time is
denoted by t
ACQ
. The converter goes from track to hold mode on the fourth falling edge of SCLK, and the analog
input signal is sampled at this time (see Figure 2).
The ADC78H89 supports idling SCLK either high or low between conversions, when CS is high. The SCLK may
also run continuously while CS is high. Regardless of whether the clock is idled, SCLK is internally gated off
when CS is brought high. If SCLK is in the low state when CS goes high, the subsequent fall of CS will generate
a falling edge of the internal version of SCLK, putting the ADC into the track mode. This is seen as the first falling
edge of SCLK. If SCLK is in the high state when CS goes high, the ADC enters the track mode on the first falling
edge of SCLK after the falling edge of CS (see Figure 2). In both cases, a total of sixteen falling edges are
required to complete the acquisition and conversion process.
Sixteen SCLK cycles are required to read a complete sample from the ADC78H89. Each bit of the sample
(including leading zeros) is valid on subsequent rising edges of SCLK. The ADC78H89 will produce four leading
zeros on DOUT, followed by twelve data bits, most significant first. The final data bit, DB0, will be clocked out on
the 16th SCLK falling edge, and will be valid on the following rising edge. Depending upon the application, the
first edge on SCLK after CS goes low may be either a falling edge or a rising edge. If the first SCLK edge after
CS goes low is a falling edge, all four leading zeros will be valid on the first four rising edges of SCLK. If the first
SCLK edge after CS goes low is a rising edge, the first leading zero may not be set up in time for a
microprocessor or DSP to read it correctly. The remaining data bits are still clocked out on the falling edges of
SCLK, so that they are valid on the rising edges of SCLK.
Control information must be written to the Control Register whenever a conversion is performed. Information is
written to the Control Register on the first eight rising edges of SCLK of each conversion. It is important that the
DIN line is set up with the correct information when reading data from the ADC78H89. The input channel to be
sampled in the next conversion process is determined by writing information to the Control Register in the current
conversion.
On the rising edges of SCLK after CS is brought low, data is loaded through the DIN pin to the Control Register,
MSB first. Since the data on the DIN pin is transferred while the conversion data is being read, 16 serial clocks
are required for each data transfer. The control register only loads the information on the first 8 rising SCLK
edges; DIN is ignored for the last 8 rising edges. Table 1 describes the bit functions, where MSB indicates the
first bit of information in the loaded data. At power-up, the control register defaults to all zeros in the bit locations.
Table 1. Control Register Bits
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
12 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: ADC78H89