Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply TSSOP 16

8 9

GND

AIN1

AIN2

AIN3

AIN4

ADC78H89

SCLK

DOUT

DIN

GND

AIN7

AIN6

AIN5

ADC78H89

www.ti.com

SNAS201D –APRIL 2003–REVISED MARCH 2013

ADC78H89 7-Channel, 500 KSPS, 12-Bit A/D Converter

Check for Samples: ADC78H89

FEATURES

DESCRIPTION

The ADC78H89 is a low-power, seven-channel

• Seven Input Channels

CMOS 12-bit analog-to-digital converter with a

• Variable Power Management

conversion throughput of 500 KSPS. The converter is

• Independent Analog and Digital Supplies

based on a successive-approximation register

architecture with an internal track-and-hold circuit. It

• SPI™/QSPI™/MICROWIRE™/DSP Compatible

can be configured to accept up to seven input signals

• Packaged in 16-Lead TSSOP

on pins AIN1 through AIN7.

The output serial data is straight binary, and is

APPLICATIONS

compatible with several standards, such as SPI™,

• Automotive Navigation

QSPI™, MICROWIRE™, and many common DSP

• Portable Systems

serial interfaces.

• Medical Instruments

The ADC78H89 may be operated with independent

• Mobile Communications

analog and digital supplies. The analog supply (AV

)

can range from +2.7V to +5.25V, and the digital

• Instrumentation and Control Systems

supply (DV

) can range from +2.7V to AV

. Normal

power consumption using a +3V or +5V supply is

KEY SPECIFICATIONS

1.5 mW and 8.3 mW, respectively. The power-down

• Conversion Rate: 500 KSPS

feature reduces the power consumption to just

0.3 µW using a +3V supply, or 0.5 µW using a +5V

• DNL: ± 1 LSB (max)

supply. The ADC78H89 is packaged in a 16-lead

• INL: ± 1 LSB (max)

TSSOP package. Operation over the industrial

• Power Consumption

temperature range of −40°C to +85°C is ensured.

– 3V Supply: 1.5 mW (typ)

– 5V Supply: 8.3 mW (typ)

Connection Diagram

Figure 1. 16-Lead TSSOP

See PW Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

PAGE 1
ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 ADC78H89 7-Channel, 500 KSPS, 12-Bit A/D Converter Check for Samples: ADC78H89 FEATURES DESCRIPTION • • • • • The ADC78H89 is a low-power, seven-channel CMOS 12-bit analog-to-digital converter with a conversion throughput of 500 KSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to seven input signals on pins AIN1 through AIN7.
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ADC78H89 SNAS201D – APRIL 2003 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Block Diagram Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 5 - 11 AIN1 to AIN7 2 NC Analog inputs. These signals can range from 0V to AVDD.
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ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) Analog Supply Voltage AVDD −0.3V to 6.5V Digital Supply Voltage DVDD −0.3V to AVDD + 0.3V, max 6.5V Voltage on Any Pin to GND −0.3V to AVDD +0.
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ADC78H89 SNAS201D – APRIL 2003 – REVISED MARCH 2013 www.ti.com ADC78H89 CONVERTER ELECTRICAL CHARACTERISTICS (1) The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, fSCLK = 8 MHz, fSAMPLE = 500 KSPS unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units (2) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes AVDD = +5.0V, DVDD = +3.
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ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 ADC78H89 CONVERTER ELECTRICAL CHARACTERISTICS (1) (continued) The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, fSCLK = 8 MHz, fSAMPLE = 500 KSPS unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions POWER SUPPLY CHARACTERISTICS (CL = 10 pF) AVDD, DVDD Typical Limits Units (2) (3) AVDD ≥ DVDD Analog and Digital Supply Voltages 2.7 V (min) 5.
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ADC78H89 SNAS201D – APRIL 2003 – REVISED MARCH 2013 www.ti.com Timing Diagrams Figure 2. ADC78H89 Operational Timing Diagram Figure 3. Timing Test Circuit CS tCONVERT tACQ t6 SCLK 1 2 3 4 Z3 Z2 Z1 7 8 16 t8 t3 Z0 DB11 DB10 DB9 DB8 DB1 DB0 t5 t4 DIN 6 t7 t2 DOUT 5 DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 4. ADC78H89 Serial Timing Diagram Figure 5.
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ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion.
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ADC78H89 SNAS201D – APRIL 2003 – REVISED MARCH 2013 www.ti.com THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time. In the case of the ADC78H89, this is 16 SCLK periods.
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ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. DNL DNL Figure 6. Figure 7. INL INL Figure 8. Figure 9. DNL vs. Supply INL vs. Supply Figure 10. Figure 11.
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ADC78H89 SNAS201D – APRIL 2003 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. 10 SNR vs. Supply THD vs. Supply Figure 12. Figure 13. ENOB vs. Supply SNR vs. Input Frequency Figure 14. Figure 15. THD vs. Input Frequency ENOB vs. Input Frequency Figure 16. Figure 17.
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ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated. Spectral Response Spectral Response Figure 18. Figure 19. Power Consumption vs. Throughput Figure 20.
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ADC78H89 SNAS201D – APRIL 2003 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION USING THE ADC78H89 An operational timing diagram and a serial interface timing diagram for the ADC78H89 are shown in the Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data.
PAGE 13
ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 Table 2. Control Register Bit Descriptions Bit #: Symbol: Description 7, 6, 2, 1, 0 DONTC Don't care. The value of this bit does not affect the device. 5 ADD2 4 ADD1 These three bits determine which input channel will be sampled and converted on the next falling edge of CS. The mapping between codes and channels is shown in Table 3. 3 ADD0 Table 3.
PAGE 14
ADC78H89 SNAS201D – APRIL 2003 – REVISED MARCH 2013 www.ti.com Figure 22. ADC78H89 in Hold Mode ADC78H89 TRANSFER FUNCTION The output format of the ADC89H89 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC78H89 is AVDD / 4096. The ideal transfer characteristic is shown in Figure 23. Figure 23. Ideal Transfer Characteristic TYPICAL APPLICATION CIRCUIT A typical application of the ADC78H89 is shown in Figure 24.
PAGE 15
ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 Figure 24. Typical Application Circuit ANALOG INPUTS An equivalent circuit for one of the ADC78H89's input channels is shown in Figure 25. At the start of each conversion, one of the ADC78H89's seven channels are selected. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should an analog input be beyond (AVDD + 300 mV) or (GND - 300 mV), as these ESD diodes will begin conducting, which could cause erratic operation.
PAGE 16
ADC78H89 SNAS201D – APRIL 2003 – REVISED MARCH 2013 www.ti.com The ADC78H89 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one exception: the ADC78H89 automatically enters power-down mode between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion (see Figure 2). The ADC78H89 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles.
PAGE 17
ADC78H89 www.ti.com SNAS201D – APRIL 2003 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC78H89CIMTX/NOPB TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC78H89CIMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.
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