Datasheet

D
OUT
CS
V
IH
t
DIS
90%
10%
90%
10%
D
OUT
90%
10%
SCLK
CS
t
CSS
1 2
t
CSH
V
IL
0.7 x V
IO
0.3 x V
IO
D
OUT
SCLK
t
DH
t
DA
ADC161S626
SNAS468C –SEPTEMBER 2008–REVISED MARCH 2013 www.ti.com
Figure 5. D
OUT
Hold and Access Times
Figure 6. Valid CS Assertion Times
Figure 7. Voltage Waveform for t
DIS
Specification Definitions
APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is
sampled for conversion.
COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input
pins are rejected.
To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed
from 2V to 3V.
CMRR = 20 LOG ( Δ Common Input / Δ Output Offset) (1)
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to
a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between Positive
Full-Scale Error and Negative Full-Scale Error and can be calculated as:
Gain Error = Positive Full-Scale Error − Negative Full-Scale Error (2)
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