Datasheet

100:
+
ADC161S626
V
REF
+IN
- IN
GND
V
A
SCLK
D
OUT
CSB
0.1 PF
10 PF
0.1 PF
+
10 PF
+5V
Controller
LM4020-2.5
V
IO
ADC161S626
www.ti.com SNAS468C –SEPTEMBER 2008–REVISED MARCH 2013
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated. The analog input should be
isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component
(e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power planes are recommended. The power planes should be
located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog power plane. All digital circuitry should be placed over the digital power plane.
Furthermore, the GND pins on the ADC161S626 and all the components in the reference circuitry and input
signal chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid
connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal
processor, or other high power digital device.
APPLICATION CIRCUITS
The following figures are examples of the ADC161S626 in typical application circuits. These circuits are basic
and will generally require modification for specific circumstances.
Data Acquisition
Figure 47 shows a typical connection diagram for the ADC161S626 operating at V
A
of +5V. V
REF
is connected to
a 2.5V shunt reference, the LM4020-2.5, to define the analog input range of the ADC161S626 independent of
supply variation on the +5V supply line. The V
REF
pin should be de-coupled to the ground plane by a 0.1 µF
ceramic capacitor and a tantalum capacitor of 10 µF. It is important that the 0.1 µF capacitor be placed as close
as possible to the V
REF
pin while the placement of the tantalum capacitor is less critical. It is also recommended
that the V
A
and V
IO
pins of the ADC161S626 be de-coupled to ground by a 0.1 µF ceramic capacitor in parallel
with a 10 µF tantalum capacitor.
Figure 47. Low cost, low power Data Acquisition System
Bridge Sensor Application
Figure 48 and Figure 49 show examples of interfacing bridge sensors to the ADC161S626. The applications
assume that the bridge sensors require buffering and amplification to fully utilize the dynamic range of the ADC
and thus optimize the performance of the entire signal path. The amplification stages consist of the LMP7732
and the LMP7731, dual and single precision amplifiers, and some gain setting passive components. The
amplification stages offer the benefit of high input impedance and high amplification capability.
Figure 49, which has the amplification stage configured as an instrumentation amplifier, has the added benefit of
additional common-mode rejection of common-mode noise or DC-voltages coming from the bridge sensor.
Depending on the voltage applied at V
CM
, the ADC161S626 in the single-ended application will convert the
output voltage of a bridge sensor that contains both a positive and negative component or a bridge sensor that
only outputs a positive voltage. For the case of a sensor with both positive and negative output capability, it is
recommended that V
CM
be connected to V
REF
. For a sensor that only outputs a positive voltage, V
CM
would need
to be connected to ground. Both of these scenarios will allow all the ADC output codes to be potentially utilized.
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