Datasheet

ADC161S626
www.ti.com SNAS468C –SEPTEMBER 2008–REVISED MARCH 2013
APPLICATIONS INFORMATION
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC161S626:
−40°C ≤ T
A
≤ +85°C
+4.5V ≤ V
A
≤ +5.5V
+2.7V ≤ V
IO
≤ +5.5V
+0.5V ≤ V
REF
≤ +5.5V
1 MHz ≤ f
SCLK
≤ 5 MHz
V
CM
: See Input Common Mode Voltage
ANALOG INPUT CONSIDERATIONS
As stated previously in Input Settling, it is not critical for the performance of the ADC161S626 to filter out the
voltage spike that occurs when the ADC161S626 enters acquisition (t
ACQ
) mode at the end of the conversion
window. However, it is critical that a system designer ensures that the transients of the spike settle out within
t
ACQ
. The burden of this task can be placed on the analog source itself or the burden can be shared by the
source and an external capacitor, C
EXT
as shown in Figure 45. The external capacitor acts as a local charge
reservoir for the internal sampling capacitor and thus reduces the size of the voltage spike. For low frequency
analog sources such as sensors with DC-like output behaviors, C
EXT
values greater than 1 nF are recommended.
However, some sensors and signal conditioning circuitry will not be able to maintain their stability in the presence
of the external capacitive load. In these instances, a series resistor (R
EXT
) is recommended. The magnitude of
R
EXT
is dependent on the output capability of the analog source and the settling requirement of the ADC.
Independent of the presence of an external capacitor, the system designer always has the option of lowering the
sample rate of the ADC161S626 which directly controls the amount of time allowed for the voltage spike to settle.
The slower the sample rate, the longer the t
ACQ
time or settling time. This is possible with the ADC161S626 since
the converter enters t
ACQ
at the end of the prior conversion and thus is tracking the analog input source the entire
time between conversions.
POWER CONSUMPTION
The architecture, design, and fabrication process allow the ADC161S626 to operate at conversion rates up to
250 kSPS while consuming very little power. The ADC161S626 consumes the least amount of power while
operating in acquisition (power-down) mode. For applications where power consumption is critical, the
ADC161S626 should be operated in acquisition mode as often as the application will tolerate. To further reduce
power consumption, stop the SCLK while CS is high.
Short Cycling
Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can
be used to lower the power consumption in those applications that do not need a full 16-bit resolution, or where
an analog signal is being monitored until some condition occurs. In some circumstances, the conversion could be
terminated after the first few bits. This will lower power consumption in the converter since the ADC161S626
spends more time in acquisition mode and less time in conversion mode.
Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC161S626
output. This is possible because the ADC161S626 places the latest converted data bit on D
OUT
as it is
generated. If only 10-bits of the conversion result are needed, for example, the conversion can be terminated by
pulling CS high after the 10
th
bit has been clocked out.
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