Datasheet

+
R
SAMPLE+
C
SAMPLE+
SW+
-
R
SAMPLE-
C
SAMPLE-
SW-
C
EXT
R
EXT+
R
EXT-
V
IN
+
-
ADC161S626
www.ti.com SNAS468C –SEPTEMBER 2008–REVISED MARCH 2013
Input Settling
When the ADC161S626 enters acquisition (t
ACQ
) mode at the end of the conversion window, the internal
sampling capacitor (C
SAMPLE
) is connected to the ADC input via an internal switch and a series resistor (R
SAMPLE
),
as shown in Figure 45. Typical values for C
SAMPLE
and R
SAMPLE
are 20 pF and 200 ohms respectively. If there is
not a large external capacitor (C
EXT
) at the analog input of the ADC, a voltage spike will be observed at the input
pins. This is a result of C
SAMPLE
and C
EXT
being at different voltage potentials. The magnitude and direction of the
voltage spike depend on the difference between the voltage of C
SAMPLE
and C
EXT
. If the voltage at C
SAMPLE
is
greater than the voltage at C
EXT
, a positive voltage spike will occur. If the opposite is true, a negative voltage
spike will occur. It is not critical for the performance of the ADC161S626 to filter out the voltage spike. Rather,
ensure that the transient of the spike settles out within t
ACQ
; for recommended solutions, see Application
Information.
Figure 45. ADC Input Capacitors
SERIAL DIGITAL INTERFACE
The ADC161S626 communicates via a synchronous 3-wire serial interface as shown in Figure 2 or re-shown in
Figure 46 for convenience. CS, chip select bar, initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of the serial data. D
OUT
is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC161S626's D
OUT
pin is in a high impedance state when CS is high and for the first clock period after CS is asserted; D
OUT
is active
for the remainder of time when CS is asserted.
The ADC161S626 samples the differential input upon the assertion of CS. Assertion is defined as bringing the
CS pin to a logic low state. For the first 17 periods of the SCLK following the assertion of CS, the ADC161S626
is converting the analog input voltage. On the 18
th
falling edge of SCLK, the ADC161S626 enters acquisition
(t
ACQ
) mode. For the next three periods of SCLK, the ADC161S626 is operating in acquisition mode where the
ADC input is tracking the analog input signal applied across +IN and -IN. During acquisition mode, the
ADC161S626 is consuming a minimal amount of power.
The ADC161S626 can enter conversion mode (t
CONV
) under three different conditions. The first condition
involves CS going low (asserted) with SCLK high. In this case, the ADC161S626 enters conversion mode on the
first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this
condition, the ADC161S626 automatically enters conversion mode and the falling edge of CS is seen as the first
falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC161S626 enters
conversion mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, there are
minimum setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
See Figure 6 in the Timing Diagram section for more information.
CS Input
The CS (chip select bar) input is active low and is CMOS compatible. The ADC161S626 enters conversion mode
when CS is asserted and the SCLK pin is in a logic low state. When CS is high, the ADC161S626 is always in
acquisition mode and thus consuming the minimum amount of power. Since CS must be asserted to begin a
conversion, the sample rate of the ADC161S626 is equal to the assertion rate of CS.
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and the characteristics of the individual device. To ensure that the MSB is always clocked out at a given time
(the 3
rd
falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in
the Timing Specification table.
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