Datasheet

ADC161S626
www.ti.com SNAS468C –SEPTEMBER 2008–REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
The ADC161S626 is a 16-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter
uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an
inherent sample-and-hold function. The differential nature of the analog inputs is maintained from the internal
sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection.
The ADC161S626 operates from independent analog and digital supplies. The analog supply (V
A
) can range
from 4.5V to 5.5V and the digital input/output supply (V
IO
) can range from 2.7V to 5.5V. The ADC161S626
utilizes an external reference (V
REF
), which can be any voltage between 0.5V and V
A
. The value of V
REF
determines the range of the analog input, while the reference input current (I
REF
) depends upon the conversion
rate.
The analog input is presented to two input pins: +IN and –IN. Upon initiation of a conversion, the differential input
at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry
while a conversion is in progress. The ADC161S626 features a zero-power track mode (ZPTM) where the ADC
is consuming the minimum amount of power (Power-Down Mode) while the internal sampling capacitor array is
tracking the applied analog input voltage. The converter enters ZPTM at the end of each conversion window and
experiences no delay when the ADC enters into Conversion Mode. This feature allows the user an easy means
for optimizing system performance based on the settling capability of the analog source while minimizing power
consumption. ZPTM is exercised by bringing chip select bar (CS) high or when CS is held low after the
conversion is complete (after the 18
th
falling edge of the serial clock).
The ADC161S626 communicates with other devices via a Serial Peripheral Interface (SPI™), a synchronous
serial interface that operates using three pins: chip select bar (CS), serial clock (SCLK), and serial data out
(D
OUT
). The external SCLK controls data transfer and serves as the conversion clock. The duty cycle of SCLK is
essentially unimportant, provided the minimum clock high and low times are met. The minimum SCLK frequency
is set by internal capacitor leakage. Each conversion requires a minimum of 18 SCLK cycles to complete. If less
than 16 bits of conversion data are required, CS can be brought high at any point during the conversion. This
procedure of terminating a conversion prior to completion is commonly referred to as short cycling.
The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit (MSB)
first, at the D
OUT
pin. The digital data that is provided at the D
OUT
pin is that of the conversion currently in
progress and thus there is no pipe line delay or latency.
REFERENCE INPUT (V
REF
)
The externally supplied reference voltage (V
REF
) sets the analog input range. The ADC161S626 will operate with
V
REF
in the range of 0.5V to V
A
.
Operation with V
REF
below 2.5V is possible with slightly diminished performance. As V
REF
is reduced, the range
of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage (V
CM
), the
differential peak-to-peak input range is limited to (2 x V
REF
).
Reducing V
REF
also reduces the size of the least significant bit (LSB). For example, the size of one LSB is equal
to [(2 x V
REF
) / 2
n
], which is 152.6 µV where n is 16 bits and V
REF
is 5V. When the LSB size goes below the noise
floor of the ADC161S626, the noise will span an increasing number of codes and overall performance will suffer.
Dynamic signals will have their SNR degrade; while, D.C. measurements will have their code uncertainty
increase. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results
of a number of consecutive conversions.
V
REF
and analog inputs (+IN and -IN) are connected to the capacitor array through a switch matrix when the input
is sampled. Hence, I
REF
, I
+IN
, and I
-IN
are a series of transient spikes that occur at a frequency dependent on the
operating sample rate of the ADC161S626.
I
REF
changes only slightly with temperature. See the curves, “Reference Current vs. SCLK Frequency” and
“Reference Current vs. Temperature” in the Typical Performance Characteristics section for additional details.
ANALOG SIGNAL INPUTS
The ADC161S626 has a differential input where the effective input voltage that is digitized is (+IN) − (−IN).
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