Datasheet
1.6V
TO OUTPUT
PIN
CL
25 pF
I
OH
I
OL
2 mA
2 mA
SCLK
CS
t
CSS
1 2
4 5 11 12 13 14 15 16
t
ACQ
(Power-Down)
t
CONV
(Power-Up)
DB13 DB12 DB5 DB4 DB3 DB2
1
D
`
SCLK
CS
2 3
17 18
0
00
1
DB1 DB0
2
t
EN
t
DIS
t
CL
t
CH
0
t
CS
ADC141S626
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
www.ti.com
ADC141S626 Timing Specifications
(1)
The following specifications apply for V
A
= V
IO
= V
REF
= +2.7V to 5.5V and f
SCLK
= 0.9 to 4.5 MHz, C
L
= 25 pF, Boldface limits
apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits Units
3 6 ns (min)
t
CSS
CS Setup Time prior to an SCLK rising edge
1/f
SCLK
- 3 1/f
SCLK
- 6 ns (max)
t
DH
D
OUT
Hold Time after an SCLK falling edge 10 6 ns (min)
t
DA
D
OUT
Access Time after an SCLK falling edge 28 40 ns (max)
t
DIS
D
OUT
Disable Time after the rising edge of CS
(2)
10 20 ns (max)
t
CS
Minimum CS Pulse Width 5 20 ns (min)
t
EN
D
OUT
Enable Time after the falling edge of CS 32 51 ns (max)
t
CH
SCLK High Time 67 89 ns (min)
t
CL
SCLK Low Time 67 89 ns (min)
t
r
D
OUT
Rise Time 7 ns
t
f
D
OUT
Fall Time 7 ns
(1) Typical values are at T
J
= 25°C and represent most likely parametric norms. Test limits are guaranteed to TI's AOQL (Average Outgoing
Quality Level).
(2) t
DIS
is the time for D
OUT
to change 10% while being loaded by the Timing Test Circuit.
Timing Diagrams
Figure 1. ADC141S626 Single Conversion Timing Diagram
Figure 2. Timing Test Circuit Figure 3. Valid CS Assertion Times
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