Datasheet
SAR CONTROL
SERIAL
INTERFACE
COMPARATOR
S/H
CDAC
+IN
-IN
V
REF
1
2
3
4
5
6
7
8
9
10
SCLK
D
OUT
GND
- IN
+IN
ADC141S626
CS
V
REF
V
A
V
IO
GND
ADC141S626
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
www.ti.com
Connection Diagram
Block Diagram
PIN DESCRIPTIONS
Pin No. Symbol Description
Voltage Reference Input. A voltage reference between 1V and V
A
must be applied to this
input. V
REF
must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.
1 V
REF
A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µFcapacitor is
recommended for enhanced performance.
Non-Inverting Input. +IN is the positive analog input for the differential signal applied to the
2 +IN
ADC141S626.
Inverting Input. −IN is the negative analog input for the differential signal applied to the
3 −IN
ADC141S626.
4 GND Ground. GND is the ground reference point for all signals applied to the ADC141S626.
5 GND Ground. GND is the ground reference point for all signals applied to the ADC141S626.
Chip Select Bar. CS must be active LOW during an SPI conversion, which begins on the
6 CS
falling edge of CS. The ADC141S626 is in acquisition mode when CS is HIGH.
Serial Data Output. The conversion result is provided on D
OUT
. The serial data output word
7 D
OUT
is comprised of 2 null bits followed by 14 data bits (MSB first). During a conversion, the
data is output on the falling edges of SCLK and is valid on the subsequent rising edges.
8 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.
Digital Input/Output Power Supply Input. A voltage source between 2.7V and 5.5V must be
9 V
IO
applied to this input. V
IO
must be decoupled to GND with a ceramic capacitor value of 0.1
µF in parallel with a bulk capacitor value of 1.0 µF to 10 µF.
Analog Power Supply Input. A voltage source between 2.7V and 5.5V must be applied to
10 V
A
this input. V
A
must be decoupled to GND with a ceramic capacitor value of 0.1 µF in
parallel with a bulk capacitor value of 1.0 µF to 10 µF.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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