Datasheet

4 5 11 12 13 14 15 16
t
ACQ
(Power-Down)
t
CONV
(Power-Up)
DB13 DB12 DB5 DB4 DB3 DB2
1
D
`
SCLK
CS
2 3
17 18
0
00
1
DB1 DB0
2
t
EN
t
DIS
t
CL
t
CH
0
t
CS
ADC141S626
SNAS434B NOVEMBER 2007REVISED MARCH 2013
www.ti.com
Data Output
The data output format of the ADC141S626 is two’s complement as shown in Figure 38. This figure indicates the
ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or
noise. Each data output bit is output on the falling edges of SCLK. The 1
st
and 2
nd
SCLK falling edges clock out
leading zeros while the 3
rd
to 16
th
SCLK falling edges clock out the conversion result, MSB first.
While most receiving systems will capture the digital output bits on the rising edges of SCLK, the falling edges of
SCLK may be used to capture the conversion result if the minimum hold time for D
OUT
is acceptable. See
Figure 6 for D
OUT
hold (t
DH
) and access (t
DA
) times.
D
OUT
is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16
th
falling edge of SCLK, the current conversion is aborted and D
OUT
will go into its high impedance state. A new
conversion will begin when CS is driven LOW.
Figure 43. ADC141S626 Single Conversion Timing Diagram
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC141S626:
40°C T
A
+85°C
+2.7V V
A
+5.5V
+2.7V V
IO
+5.5V
1V V
REF
V
A
0.9 MHz f
SCLK
4.5 MHz
V
CM
: See Input Common Mode Voltage
POWER CONSUMPTION
The architecture, design, and fabrication process allow the ADC141S626 to operate at conversion rates up to
250 kSPS while consuming very little power. The ADC141S626 consumes the least amount of power while
operating in acquisition (power-down) mode. For applications where power consumption is critical, the
ADC141S626 should be operated in acquisition mode as often as the application will tolerate. To further reduce
power consumption, stop the SCLK while CS is high.
Short Cycling
Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can
be used to lower the power consumption in those applications that do not need a full 14-bit resolution, or where
an analog signal is being monitored until some condition occurs. In some circumstances, the conversion could be
terminated after the first few bits. This will lower power consumption in the converter since the ADC141S626
spends more time in acquisition mode and less time in conversion mode.
Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC141S626
output. This is possible because the ADC141S626 places the latest converted data bit on D
OUT
as it is
generated. If only 10-bits of the conversion result are needed, for example, the conversion can be terminated by
pulling CS high after the 10
th
bit has been clocked out.
18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADC141S626