Datasheet
|
|
|
01 1111 1111 1111b
|
|
|
10 0000 0000 0000b
00 0000 0000 0000b
ADC Output Code
Analog Input
-1 LSB
+1 LSB
+V
REF
±1LSB
-V
REF
+1LSB
ADC141S626
www.ti.com
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
ANALOG SIGNAL INPUTS
The ADC141S626 has a differential input where the effective input voltage that is digitized is (+IN) − (−IN). By
using this differential input, small signals common to both inputs are rejected. As shown in Figure 37, noise is
immune at low frequencies where the common-mode rejection ratio (CMRR) is 90 dB. As the frequency
increases to 1 MHz, the CMRR rolls off to 40 dB . In general, operation with a fully differential input signal or
voltage will provide better performance than with a single-ended input. However, if desired, the ADC141S626
can be presented with a single-ended input.
Figure 37. Analog Input CMRR vs. Frequency
The current required to recharge the input sampling capacitor will cause voltage spikes at +IN and −IN. Do not
try to filter out these noise spikes. Rather, ensure that the transient settles out during the acquisition period.
Differential Input Operation
As shown in Figure 38 for a fully differential input signal, a positive full scale output code (01 1111 1111 1111b or
1FFFh or 8191d) will be obtained when (+IN) − (−IN) is greater than or equal to (V
REF
− 1 LSB). A negative full
scale code (10 0000 0000 0000b or 2000h or -8192d) will be obtained when (+IN) − (−IN) is less than or equal to
(−V
REF
+ 1 LSB). This ignores gain, offset and linearity errors, which will affect the exact differential input voltage
that will determine any given output code. Both inputs should be biased at a common mode voltage (V
CM
), which
will be thoroughly discussed in Input Common Mode Voltage . Figure 39 shows the ADC141S626 being driven
by a full-scale differential source.
Figure 38. ADC Output vs. Input for a Differential Input Operation
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: ADC141S626