Datasheet
ADC141S626
SNAS434B –NOVEMBER 2007–REVISED MARCH 2013
www.ti.com
FUNCTIONAL DESCRIPTION
The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter
uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an
inherent sample-and-hold function. The differential nature of the analog inputs is maintained from the internal
sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection.
The ADC141S626 operates from independent analog and digital supplies. The analog supply (V
A
) can range
from 2.7V to 5.5V and the digital input/output supply (V
IO
) can range from 2.7V to 5.5V. The ADC141S626
utilizes an external reference (V
REF
), which can be any voltage between 1V and V
A
. The value of V
REF
determines the range of the analog input, while the reference input current (I
REF
) depends upon the conversion
rate.
The analog input is presented to two input pins: +IN and –IN. Upon initiation of a conversion, the differential input
at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry
while a conversion is in progress. The ADC141S626 features a zero-power track mode where the ADC is
consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied
analog input voltage. Zero-power track mode is exercised by bringing chip select bar (CS) high or low after the
conversion is complete (after the 16
th
falling edge of the serial clock).
The ADC141S626 communicates with other devices via Serial Peripheral Interface (SPI™) , a synchronous serial
interface that operates using three pins: chip select bar (CS), serial clock (SCLK), and serial data out (D
OUT
). The
external SCLK controls data transfer and serves as the conversion clock. The duty cycle of SCLK is essentially
unimportant, provided the minimum clock high and low times are met. The minimum SCLK frequency is set by
internal capacitor leakage. Each conversion requires 18 SCLK cycles to complete. If less than 14 bits of
conversion data are required, CS can be brought high at any point during the conversion. This procedure of
terminating a conversion prior to completion is commonly referred to as short cycling.
The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit (MSB)
first, at the D
OUT
pin. The digital data that is provided at the D
OUT
pin is that of the conversion currently in
progress and thus there is no pipe line delay.
REFERENCE INPUT (V
REF
)
The externally supplied reference voltage (V
REF
) sets the analog input range. The ADC141S626 will operate with
V
REF
in the range of 1V to V
A
.
Operation with V
REF
below 1V is also possible with slightly diminished performance. As V
REF
is reduced, the
range of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage (V
CM
), the
differential peak-to-peak input range is limited to (2 x V
REF
). See Input Common Mode Voltage for more details.
Reducing V
REF
also reduces the size of the least significant bit (LSB). The size of one LSB is equal to [(2 x V
REF
)
/ 2
n
], which is 16,384 where n is 14 bits. When the LSB size goes below the noise floor of the ADC141S626, the
noise will span an increasing number of codes and overall performance will suffer. For example, dynamic signals
will have their SNR degrade, while D.C. measurements will have their code uncertainty increase. Since the noise
is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of
consecutive conversions.
Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D
converter will increase in terms of LSB size as V
REF
is reduced.
V
REF
and analog inputs (+IN and -IN) are connected to the capacitor array through a switch matrix when the input
is sampled. Hence, I
REF
, I
+IN
, and I
-IN
are a series of transient spikes that occur at a frequency dependent on the
operating sample rate of the ADC141S626.
I
REF
changes only slightly with temperature. See Figure 31 and Figure 32 in Typical Performance Characteristics
for additional details.
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